參數(shù)資料
型號(hào)： RS5C372B-E1
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： I2C-bus Serial Interface Real Time Clock (8pin SSOP)
中文描述： REAL TIME CLOCK, PDSO8
封裝： 0.65 MM PITCH, SSOP-8
文件頁(yè)數(shù)： 15/39頁(yè)
文件大?。?/td> 474K
代理商： RS5C372B-E1
RS5C372B
- 15 -
Any registered imaginary time should be replaced with correct time as carrying to such registered
imaginary time digits from lower-order ones cause the clock counter malfunction.
2.6. Time Trimming Register (Internal address at 7h)
D7
D6
D5
D4
D3
D2
D1
D0
/XSL
F6
F5
F4
F3
F2
F1
F0
(for write operation)
/XSL
0
*)The default means read values when XSTP=”1” by after initial power-on or supply voltage drop,etc.
F6
0
F5
0
F4
0
F3
0
F2
0
F1
0
F0
0
(for read operation)
Default(*)
2.6.1. /XSL bit
The /XSL bit is used to select a crystal oscillator.
Set the /XSL to “0” (default) to use 32.768kHz.
Set the /XSL to “1” to use 32.000kHz.
2.6.2 F6 to F0
The Time Trimming Circuit adjust one second count based on this register readings when second digit is
00, 20, or 40 seconds. Normally, counting up to seconds is made once per 32768 of clock pulse (or
32000 when 32.000kHz crystal is used) generated by the oscillator. Setting data to this register activates
the time trimming circuit.
Register counts will be incremented as ((F5, F4, F3, F2, F1, F0)-1) x 2 when F6 is set to “0”.
Register counts will be decremented as ((/F5, /F4, /F3, /F2, /F1, /F0)+1) when F6 is set to “1”.
Counts will not change when (F6, F5, F4, F3, F2, F1, F0) are set to (*, 0, 0, 0, 0, 0, *).
For example, when 32.768kHz crystal is used.
When (F6, F5, F4, F3, F2, F1, F0) are set to (0, 0, 0, 0, 1, 1, 1), counts will change as:32768+(7-1) x
2=32780 (clock will be delayed) when second digit is 00, 20, or 40.
When (F6, F5, F4, F3, F2, F1, F0) are set to (0, 0, 0, 0, 0, 0, 1), counts will remain 32768 without changing
when second digit is 00, 20, or 40.
When (F6, F5, F4, F3, F2, F1, F0) are set to (1, 1, 1, 1, 1, 1, 0), counts will change as:32768+(-2) x
2=32.764 (clock will be advanced) when second digit is 00, 20, or 40.
Adding 2 clock pulses every 20 seconds:2/(32.768 x 20)=3.051ppm (or 3.125ppm when 32.000kHz crystal
is used), delays the clock by approx. 3ppm. Likewise, decrementing 2 clock pulses advances the clock
by 3ppm. Thus the clock may be adjusted to the precision of ±1.5ppm.
Note : The clock adjust function only adjust clock timing.
Oscillation frequency and 32kHz clock output is not adjusted.
2.7. Alarm_A, Alarm_B Register (Alarm_A: Internal address at 8-Ah,Alarm_B: Internal address at B-Dh)
2.7.1. Alarm_A, Alarm_B Minute Register (Alarm_A: Internal address at 8h, Alarm_B: Internal address at Bh)
D7
D6
D5
D4
D3
D2
D1
D0
-
AM40(*1)
AM20
AM10
AM8
AM4
AM2
AM1
(for write operation)
0
0
AM40
unde-
fined
AM20
unde-
fined
AM10
unde-
fined
AM8
unde-
fined
AM4
unde-
fined
AM2
unde-
fined
AM1
unde-
fined
(for read operation)
Default(*2)
*1) AXXX in this table is the name for Alarm_A function, for Alarm_B function it is BXXX.
*2) The default means read values when XSTP=“1” by after initial power-on or supply voltage drop,etc.
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