參數(shù)資料
型號(hào)： RS5C372B-E1
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： I2C-bus Serial Interface Real Time Clock (8pin SSOP)
中文描述： REAL TIME CLOCK, PDSO8
封裝： 0.65 MM PITCH, SSOP-8
文件頁(yè)數(shù)： 28/39頁(yè)
文件大?。?/td> 474K
代理商： RS5C372B-E1
RS5C372B
- 28 -
4.1. Control of the /INTR output (flag bit, enable bit)
Of the two output wave forms listed above, interrupt output conditions may be set by setting the flag bit that
monitors output state on the register, the enable bit that enables an output wave form.
Flag bit
Enable bit
Alarm_A
AAFG
(D1 at internal address Fh)
BAFG
(D0 at internal address Fh)
CTFG
(D2 at internal address Fh)
AALE
(D7 at internal address Eh)
BALE
(D6 at internal address Eh)
Disabled at CT2=CT1=CT0=0
(D2-0 at internal address Eh)
Alarm_B
Periodic
Interrupt
When power ON (XSTP=1) since AALE=BALE=CT2=CT1=CT0=0, /INTR=OFF (H).
When more than one output wave forms are output from a single output pin, the output will have or wave
form of negative logic of both.
Example:When Alarm_A and Alarm_B are output from the /INTR pin.
/Alarm_B
/INTR
/Alarm_A
In such a case which output wave form is output from the pin may be confirmed by reading the flag bits.
4.2. Alarm Interrupt
For setting an alarm time, designated time such as day-of-the-week, hour or minute should be set to the
alarm registers being AALE (BALE) bit to 0. After that set the AALE (BALE) bit to 1, from this moment
onward when such registered alarm time coincide the value of calendar counter the /INTR
comes down to “L” (ON). The /INTR output can be controlled by operating to the AALE
BALE) and AAFG (BAFG) bits.
Alarm-calendar
coincidence(1min.)
A
←
→
AALE
←
1
(BALE)
A: MAX61.1
μ
s
(MAX62.5
μ
s when 32.000kHz crystal is used.)
/INTR
AALE
←
0
(BALE)
AALE
←
1
(BALE)
AALE
←
0
(BALE)
/INTR
AAFG
←
0
(BAFG)
AALE
←
1
(BALE)
Day-of-the-
week, time
matched
Day-of-the-
week, time
matched
Day-of-the-
week, time
matched
Day-of-the-
week, time
matched
) Note that AAFG (BAFG) has an output wave form of reversed logic.
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