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參數(shù)資料
| 型號： | RS5C372B-E2 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | I2C-bus Serial Interface Real Time Clock (8pin SSOP) |
| 中文描述： | REAL TIME CLOCK, PDSO8 |
| 封裝： | 0.65 MM PITCH, SSOP-8 |
| 文件頁數(shù)： | 12/39頁 |
| 文件大?。?/td> | 474K |
| 代理商： | RS5C372B-E2 |
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RS5C372B
- 12 -
Time Display Digit Table
24-hour time
display system
00
01
02
03
04
05
06
07
08
09
10
11
*) Either the 12-hour or 24-hour time display system should be selected before writing time data.
12-hour time
display system
12 (AM12)
01 (AM 1)
02 (AM 2)
03 (AM 3)
04 (AM 4)
05 (AM 5)
06 (AM 6)
07 (AM 7)
08 (AM 8)
09 (AM 9)
10 (AM10)
11 (AM11)
24-hour time
display system
12
13
14
15
16
17
18
19
20
21
22
23
12-hour time
display system
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
2.2.2. ADJ
±
30 Second Adjust Bit
ADJ
0
1
Description
Ordinary operation
Second digit adjustment
The following operations are performed by setting the second ADJ bit to 1.
1) For second digits ranging from “00” to “29” seconds:
Time counters smaller than seconds are reset and second digits are set to “00”.
2) For second digits ranging from “30” to “59” seconds:
Time counters smaller than seconds are reset and second digits are set to “00”. Minute digits
are incremented by 1.
Second digits are adjusted within 122μs (within 125μs:when 32.000kHz crystal is used) from writing
operation to ADJ.
The ADJ bit is for write only and allows no read operation.
2.2.3. XSTP
Oscillator Halt Sensing Bit
XSTP
0
1
Description
Ordinary oscillation
Oscillator halt sensing
(Default)
The XSTP bit senses the oscillator halt.
When oscillation is halted after initial power on from 0V or drop in supply voltage the bit is set to “1”
and which remains to be “1” after it is restarted. This bit may be used to judge validity of clock and
calendar count data after power on or supply voltage drop.
When this bit is set to “1”, /XSL, F6-F0, CT2, CT1, CT0, AALE, BALE, /CLEN and TEST bits are
reset to “0”. /INTR will stop output and the 32KOUT outputs 32kHz clock pulses.
The XSTP bit is set to "0" by setting some data to the control register 2 (address Fh) during ordinary
oscillation.
2.2.4. /CLEN
32kHz Clock Output Bit
/CLEN
0
1
Description
32kHz clock output enabled
32kHz clock output disabled
(Default)
By setting this bit to “0”, output of clock pulses of the same frequency as the crystal oscillator from
32KOUT pin, is enabled.
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