參數(shù)資料
型號(hào)： RS5C372B-E2
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： I2C-bus Serial Interface Real Time Clock (8pin SSOP)
中文描述： REAL TIME CLOCK, PDSO8
封裝： 0.65 MM PITCH, SSOP-8
文件頁(yè)數(shù)： 19/39頁(yè)
文件大?。?/td> 474K
代理商： RS5C372B-E2
RS5C372B
- 19 -
transmission. When the master is the receiver, it generates no acknowledge signal after the last 1 byte of data
from the slave to tell the transmitter that data transmission has completed when the slave side (transmitter)
continues to release the SDA pin so that the master will be able to generate Stop Condition.
SCL
from master
SDA
from transmitter
SDA
from reciever
1
2
8
9
Acknowledge
signal
Start
Condition
1.2.3. Data transmission format in I
2
C-bus
2
C-bus generates no CE signals. In place of it each device has a 7bit slave address allocated. The first 1byte
is allocated to this 7bit of slave address and to the command (R/W) for which data transmission direction is
designated by the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2
and after bytes are read, when 8bit is “H” and write when “L”.
The slave address of the RS5C372B is specified at (0110010).
At the end of data transmission/receiving stop condition is generated to complete transmission. However, if
start condition is generated without generating Stop Condition, Repeated Start Condition is met and
transmission/receiving data may be continued by setting the slave address again. Use this procedures when
the transmission direction needs to be changed during one transmission.
S
A
A
Data
/A P
Data is written into the slave
from the master
S
0
A
A
A P
When data is read from the
slave immediately after 7bit
addressing from the master
from master to slave
from slave to master
Sr
Repeated Start Condition
P
Stop Condition
A
A
/A
Acknowledge
R/W=1(Read)
(0110010)
Inform read has been completed by not generating
an acknowledge signal, to the slave side.
Data
R/W=0(Write)
(0110010)
When
direction is to be changed
during transmission.
the
transmission
Sr
1
0
A
A
R/W=0(Write)
A
Data
R/W=1(Read)
(0110010)
S
1
A
/A P
Inform read has been completed by not generating
an acknowledge signal, to the slave side.
Data
S
Start Condition
(0110010)
Slave Address
Slave Address
Data
Slave Address
Slave Address
Data
Data
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