參數(shù)資料
型號： RTL8100
廠商： Electronic Theatre Controls, Inc.
英文描述： REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 瑞昱單芯片快速以太網(wǎng)控制器電源管理
文件頁數(shù)： 22/58頁
文件大?。?/td> 657K
代理商： RTL8100
RTL8100B(L)
2001-11-9
Rev.1.41
22
5.13 CONFIG 3: Configuration Register3
(Offset 0059h, R/W)
Bit
7
R/W
R
Symbol
GNTSel
Description
Gnt Select:
Select the Frame’s asserted time after the Grant signal has
been asserted. The Frame and Grant are the PCI signals.
1: delay one clock from GNT assertion.
0: No delay
Parameter Enable:
(Used in 100Mbps mode only)
This set to 0 and the 9346CR register EEM1=EEM0=1 will enable the
PHY1_PARM, PHY2_PARM, and TW_PARM registers to be written via
software.
This set to 1 will allow parameters to be auto-loaded from the 93C46
and disable writing to the PHY1_PARM, PHY2_PARM and
TW_PARM registers via software.
The PHY1_PARM and PHY2_PARM can be auto-loaded from the
EEPROM in this mode. The parameter auto-load process is executed
every time the Link is OK in 100Mbps mode.
Magic Packet:
This bit is valid when the PWEn bit of the CONFIG1
register is set. The RTL8100B(L) will assert the PMEB signal to
wakeup the operating system when the Magic Packet is received.
Once the RTL8100B(L) has been enabled for Magic Packet wakeup
and has been put into adequate state, it scans all incoming packets
addressed to the node for a specific data sequence, which indicates to
the controller that this is a Magic Packet frame. A Magic Packet frame
must also meet the basic requirements of:
Destination address + Source address + data + CRC
The destination address may be the node ID of the receiving station or a
multicast address, which includes the broadcast address.
The specific sequence consists of 16 duplications of 6 byte ID registers,
with no breaks or interrupts. This sequence can be located anywhere
within the packet, but must be preceded by a synchronization stream, 6
bytes of FFh. The device will also accept a multicast address, as long as
the 16 duplications of the IEEE address match the address of the ID
registers.
If the Node ID is 11h 22h 33h 44h 55h 66h, then the magic frame’s
format is similar to the following:
Destination address + source address + MISC + FF FF FF FF FF FF +
MISC + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 +
11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33
44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66
+ 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33
44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + MISC + CRC
Link Up:
This bit is valid when the PWEn bit of CONFIG1 register is
set. The RTL8100B(L), in adequate power state, will assert the PMEB
signal to wakeup the operating system when the cable connection is
re-established.
Reserved
Fast Back to Back Enable:
Set to 1 to enable Fast Back to Back.
6
R/W
PARM_En
5
R/W
Magic
4
R/W
LinkUp
3-1
0
-
R
-
FBtBEn
相關(guān)PDF資料
PDF描述
RTL8100B REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100BL REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100BLLQTP REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100BQFP REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100L REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RTL8100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100B(L) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RTL8100B(L) Specification
RTL8100BL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100BLLQTP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100BQFP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
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