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RTL8100B(L)
2001-11-9
Rev.1.41
2
1. Features
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100 pin QFP/LQFP
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Integrated Fast Ethernet MAC, Physical chip and
transceiver in one chip
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10 Mb/s and 100 Mb/s operation
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Supports 10 Mb/s and 100 Mb/s N-way
Auto-negotiation operation
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PCI local bus single-chip Fast Ethernet controller
Compliant to PCI Revision 2.2
Supports PCI clock 16.75MHz-40MHz
Supports PCI target fast back-to-back transaction
Provides PCI bus master data transfers and PCI
memory space or I/O space mapped data transfers
of RTL8100B(L)'s operational registers
Supports PCI VPD (Vital Product Data)
Supports ACPI, PCI power management
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Supports 25MHz crystal or 25MHz OSC as the internal
clock source. The frequency deviation of either crystal or
OSC must be within 50 PPM.
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Compliant to PC99/PC2001 standard
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Supports Wake-On-LAN function and remote wake-up
(Magic Packet*, LinkChg and Microsoft
wake-up frame)
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Supports 4 Wake-On-LAN (WOL) signals (active high,
active low, positive pulse, and negative pulse)
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Supports auxiliary power-on internal reset, to be ready
for remote wake-up when main power still remains off
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Supports auxiliary power auto-detect, and sets the
related capability of power management registers in PCI
configuration space.
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Includes a programmable, PCI burst size and early
Tx/Rx threshold.
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Supports a 32-bit general-purpose timer with the
external PCI clock as clock source, to generate
timer-interrupt
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Contains two large (2Kbyte) independent receive and
transmit FIFOs
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Advanced power saving mode when LAN function or
wakeup function is not used
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Uses 93C46 (64*16-bit EEPROM) to store resource
configuration, ID parameter, and VPD data.
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Supports LED pins for various network activity
indications
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Supports loopback capability
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Half/Full duplex capability
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Supports Full Duplex Flow Control (IEEE 802.3x)
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2.5/3.3V power supply with 5V tolerant I/Os.
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0.25u CMOS process
* Third-party brands and names are the property of their
respective owners.
Note: The model number of the QFP package is RTL8100B. The LQFP package model number is RTL8100BL.