參數(shù)資料
型號(hào)： RTL8100BQFP
廠商： Electronic Theatre Controls, Inc.
英文描述： REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 瑞昱單芯片快速以太網(wǎng)控制器電源管理
文件頁數(shù)： 11/58頁
文件大小： 657K
代理商： RTL8100BQFP
RTL8100B(L)
2001-11-9
Rev.1.41
11
0052h
0053H
0054h-0057h
R/W
-
R /W
CONFIG1
-
TimerInt
Configuration Register 1
Reserved
Timer Interrupt Register:
Once having written a nonzero value to
this register, the Timeout bit of the ISR register will be set whenever
the TCTR reaches to this value. The Timeout bit will never be set as
long as the TimerInt register is zero.
Media Status Register
Configuration register 3
Configuration register 4
Reserved
Multiple Interrupt Select
PCI Revision ID = 10h.
Reserved
Transmit Status of All Descriptors
Basic Mode Control Register
Basic Mode Status Register
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Register
Auto-Negotiation Expansion Register
Disconnect Counter
False Carrier Sense Counter
N-way Test Register
RX_ER Counter
CS Configuration Register
Reserved
PHY parameter 1
Twister parameter
PHY parameter 2
Reserved
Power Management CRC register0 for wakeup frame0
Power Management CRC register1 for wakeup frame1
Power Management CRC register2 for wakeup frame2
Power Management CRC register3 for wakeup frame3
Power Management CRC register4 for wakeup frame4
Power Management CRC register5 for wakeup frame5
Power Management CRC register6 for wakeup frame6
Power Management CRC register7 for wakeup frame7
Power Management wakeup frame0 (64bit)
Power Management wakeup frame1 (64bit)
Power Management wakeup frame2 (64bit)
Power Management wakeup frame3 (64bit)
Power Management wakeup frame4 (64bit)
Power Management wakeup frame5 (64bit)
Power Management wakeup frame6 (64bit)
Power Management wakeup frame7 (64bit)
LSB of the mask byte of wakeup frame0 within offset 12 to 75
LSB of the mask byte of wakeup frame1 within offset 12 to 75
LSB of the mask byte of wakeup frame2 within offset 12 to 75
LSB of the mask byte of wakeup frame3 within offset 12 to 75
LSB of the mask byte of wakeup frame4 within offset 12 to 75
LSB of the mask byte of wakeup frame5 within offset 12 to 75
0058h
0059h
005Ah
005Bh
R/W
R/W
R/W
-
R/W
R
-
R
R/W
R
R/W
R
R
R
R
R/W
R
R/W
-
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSR
CONFIG3
CONFIG4
-
MULINT
RERID
-
TSAD
BMCR
BMSR
ANAR
ANLPAR
ANER
DIS
FCSC
NWAYTR
REC
CSCR
-
PHY1_PARM
TW_PARM
PHY2_PARM
-
CRC0
CRC1
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7
Wakeup0
Wakeup1
Wakeup2
Wakeup3
Wakeup4
Wakeup5
Wakeup6
Wakeup7
LSBCRC0
LSBCRC1
LSBCRC2
LSBCRC3
LSBCRC4
LSBCRC5
005Ch-005Dh
005Eh
005Fh
0060h-0061h
0062h-0063h
0064h-0065h
0066h-0067h
0068h-0069h
006Ah-006Bh
006Ch-006Dh
006Eh-006Fh
0070h-0071h
0072h-0073h
0074h-0075h
0076-0077h
0078h-007Bh
007Ch-007Fh
0080h
0081-0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch–0093h
0094h–009Bh
009Ch–00A3h
00A4h–00ABh
00ACh–00B3h
00B4h–00BBh
00BCh–00C3h
00C4h–00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
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