參數(shù)資料
型號(hào)： RTL8100BQFP
廠商： Electronic Theatre Controls, Inc.
英文描述： REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 瑞昱單芯片快速以太網(wǎng)控制器電源管理
文件頁(yè)數(shù)： 18/58頁(yè)
文件大?。?/td> 657K
代理商： RTL8100BQFP
RTL8100B(L)
2001-11-9
Rev.1.41
18
15-13
R/W
RXFTH2, 1, 0
Rx FIFO Threshold:
Specifies Rx FIFO Threshold level. When the
number of the received data bytes from a packet, which is being received
into the RTL8100B(L)'s Rx FIFO, has reached to this level (or the FIFO
has contained a complete packet), the receive PCI bus master function
will begin to transfer the data from the FIFO to the host memory. This
field sets the threshold level according to the following table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = No Rx threshold. The RTL8100B(L) begins the transfer of data
after having received a whole packet in the FIFO.
Rx Buffer Length:
This field indicates the size of the Rx ring buffer.
00 = 8k + 16 byte
01 = 16k + 16 byte
10 = 32K + 16 byte
11 = 64K + 16 byte
Max DMA Burst Size per Rx DMA Burst:
This field sets the maximum
size of the receive DMA data bursts according to the following table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = Unlimited
When set to 0: The RTL8100B(L) will transfer the rest of the packet data into
the beginning of the Rx buffer if this packet has not been completely moved
into the Rx buffer and the transfer has arrived at the end of the Rx buffer.
When set to 1: The RTL8100B(L) will keep moving the rest of the packet
data into the memory immediately after the end of the Rx buffer, if this
packet has not been completely moved into the Rx buffer and the transfer
has arrived at the end of the Rx buffer. The software driver must reserve at
least 1.5K bytes buffer to accept the remainder of the packet. We assume
that the remainder of the packet is X bytes. The next packet will be moved
into the memory from the X byte offset at the top of the Rx buffer.
This bit is invalid when Rx buffer is selected to 64K bytes.
Reserved
Accept Error Packet:
When set to 1, all packets with CRC error,
alignment error, and/or collided fragments will be accepted. When set to 0,
all packets with CRC error, alignment error, and/or collided fragments will
be rejected.
Accept Runt:
This bit allows the receiver to accept packets that are
smaller than 64 bytes. The packet must be at least 8 bytes long to be
accepted as a runt. Set to 1 to accept runt packets.
Accept Broadcast packets:
Set to 1 to accept, 0 to reject.
Accept Multicast packets:
Set to 1 to accept, 0 to reject.
Accept Physical Match packets:
Set to 1 to accept, 0 to reject.
Accept All Packets:
Set to 1 to accept all packets with a physical
destination address, 0 to reject.
12-11
R/W
RBLEN1, 0
10-8
R/W
MXDMA2, 1, 0
7
R/W
WRAP
6
5
-
-
R/W
AER
4
R/W
AR
3
2
1
0
R/W
R/W
R/W
R/W
AB
AM
APM
AAP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RTL8100C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100CL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100C-LF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100CL-LF 制造商:Realtek Semiconductor 功能描述:RTL8100CL Series 3.6 V Fast Ethernet Controller with Power Management LQFP-128
RTL8100L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
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