參數(shù)資料
型號(hào)： S-8233CAFT
元件分類： 電源管理
英文描述： 3-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16
封裝： TSSOP-16
文件頁(yè)數(shù)： 5/26頁(yè)
文件大?。?/td> 440K
代理商： S-8233CAFT
Battery Protection IC(for a 3-serial-cell pack)
Rev.3.1_00
S-8233C Series
Seiko Instruments Inc.
13
the normal condition. At that time, output voltage of CSO goes ‘Low’.
Over discharge condition
If any one of the battery voltages falls below the over discharge detection voltage (VDD) during
discharging under normal condition and it continues for the over discharge detection delay time (tDD) or
longer, the discharging FET turns off and discharging stops. This condition is called the over discharge
condition. In this condition, output voltage of DSO goes ‘High’. When the discharging FET turns off, the
VMP terminal voltage becomes equal to the VSS voltage and the IC's current consumption falls below
the power-down current consumption (IPDN). This condition is called the power-down condition. The
VMP and VSS terminals are shorted by the Rvsm resistor under the over discharge and power-down
conditions.
The power-down condition is canceled when the charger is connected and the voltage between VMP
and VSS is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes
equal to or higher than the over discharge release voltage (VDU) in this condition, the over discharge
condition changes to the normal condition. In this condition, output voltage of DSO goes ‘Low’.
Delay circuits
The over charge detection delay time (tCU1 to tCU3), over discharge detection delay time (tDD1 to
TDD3), and over current detection delay time 1 (tI0V1) are changed with external capacitors (C4 to C6).
The delay times are calculated by the following equations:
Min Typ. Max.
TCU[S] =Delay factor ( 1.07, 2.13, 3.19)×C4 [uF]
TDD[S] =Delay factor ( 0.20, 0.40, 0.60)×C5 [uF]
TIOV1[S]=Delay factor ( 0.10, 0.20, 0.30)×C6 [uF]
Note: The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time
cannot be changed via an external capacitor.
CTL terminal
If the CTL terminal is floated under normal condition, it is pulled up to the VCC potential in the IC, and
both the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and
discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time,
the VMP and VCC terminals are shorted by the Rvcm resistor.
When the CTL terminal becomes equal to VSS potential, charging and discharging are enabled and go
back to their appropriate conditions for the battery voltages.
0V battery charging function
This function is used to recharge the three serially-connected batteries after they self-discharge to 0V.
When the 0V charging start voltage (V0CHAR) or higher is applied to between VMP and VSS by
connecting the charger, the charging FET gate is fixed to VSS potential.
When the voltage between the gate sources of the charging FET becomes equal to or higher than the
turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the
discharging FET turns off and the charging current flows through the internal parasitic diode in the
discharging FET. If all the battery voltages become equal to or higher than the over discharge release
voltage (VDU), the normal condition returns.
Notes: In the products without 0V battery charging function, the resistance between VCC and VMP and
between VSS and VMP are lower than the products with 0V battery charging function. It causes to
that over charge detection voltage increases by the drop voltage of R5 (see Figure 7 for a
相關(guān)PDF資料
PDF描述
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S-8233CAFT-TB-G 功能描述:電池管理 4.25V 3-Cell Serial RoHS:否 制造商:Texas Instruments 電池類型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel
S82343 制造商:Intel 功能描述:
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