參數(shù)資料
型號(hào): S10202-16
廠商: Hamamatsu Photonics
英文描述: Back-thinned TDI-CCD Operating the back-thinned CCD in TDI mode delivers high sensitivity.
中文描述: 回到清淡TDI發(fā)動(dòng)機(jī),防治荒漠化工作的后臺(tái)薄TDI的模式在防治荒漠化公約提供高靈敏度。
文件頁(yè)數(shù): 9/11頁(yè)
文件大?。?/td> 232K
代理商: S10202-16
Back-thinned TDI-CCD
S10200-02, S10201-04, S10202-08, S10202-16
9
S10202-08
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Symbol
P2V
P3V
P1V
TGa
DGND
OFG
OFD
RD
OD
AGND
OSa1
-
OSa2
-
OSa3
-
OSa4
-
AGND
OG
DGND
RGa1
SGa1
Function
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Symbol
P2V
P3V
P1V
TGb
SGb2
RGb2
DGND
OFG
OFD
OG
RD
OD
AGND
-
OSb8
-
OSb7
-
OSb6
-
OSb5
AGND
DGND
Function
CCD vertical register clock-2
CCD vertical register clock-3
CCD vertical register clock-1
Transfer gate-a
Digital GND
Overflow gate
Overflow drain
Reset drain
Output drain
Analog GND
Output transistor source-a1
CCD vertical register clock-2
CCD vertical register clock-3
CCD vertical register clock-1
Transfer gate-b
Summing gate-b 2
Reset gate-b 2
Digital GND
Overflow gate
Overflow drain
Output gate
Reset drain
Output drain
Analog GND
Output transistor source-a2
Output transistor source-a3
Output transistor source-b8
Output transistor source-a4
Output transistor source-b7
Analog GND
Output gate
Digital GND
Reset gate-a 1
Summing gate-a 1
CCD horizontal register-a1
clock-
CCD horizontal register-a1
clock-2
CCD horizontal register-a2
clock-2
CCD horizontal register-a2
clock-1
Digital GND
Analog GND
Output transistor source-a5
Output transistor source-b6
Output transistor source-b5
Analog GND
Digital GND
CCD horizontal register-b2
clock-
CCD horizontal register-b2
clock-2
CCD horizontal register-b1
clock-2
CCD horizontal register-b1
clock-
Summing gate-b 1
Reset gate-b 1
Digital GND
Output gate
Analog GND
24
P1Ha1
74
P1Hb2
25
P2Ha1
75
P2Hb2
26
P2Ha2
76
P2Hb1
27
P1Ha2
77
P1Hb1
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DGND
AGND
OSa5
-
OSa6
-
OSa7
-
OSa8
-
AGND
OD
RD
OG
OFD
OFG
DGND
RGa2
SGa2
TGa
P1V
P3V
P2V
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SGb1
RGb1
DGND
OG
AGND
-
OSb4
-
OSb3
-
OSb2
-
OSb1
AGND
OD
RD
OFD
OFG
DGND
TGb
P1V
P3V
P2V
Output transistor source-a6
Output transistor source-a7
Output transistor source-b4
Output transistor source-a8
Output transistor source-b3
Analog GND
Output drain
Reset drain
Output gate
Overflow drain
Overflow gate
Digital GND
Reset gate-a 2
Summing gate-a 2
Transfer gate-a
CCD vertical register clock-1
CCD vertical register clock-3
CCD vertical register clock-2
Output transistor source-b2
Output transistor source-b1
Analog GND
Output drain
Reset drain
Overflow drain
Overflow gate
Digital GND
Transfer gate-b
CCD vertical register clock-1
CCD vertical register clock-3
CCD vertical register clock-2
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