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參數(shù)資料
| 型號(hào)： | S12BKPV1D |
| 廠商： | Motorola, Inc. |
| 英文描述： | MC9S12DT128 Device User Guide V02.09 |
| 中文描述： | MC9S12DT128設(shè)備的用戶手冊(cè)V02.09 |
| 文件頁數(shù)： | 21/138頁 |
| 文件大?。?/td> | 2083K |
| 代理商： | S12BKPV1D |
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MC9S12DT128 Device User Guide — V02.09
21
–
The Byteflight pin functionality (BF_PSLM, BF_PERR, BF_PROK, BF_PSYN, TX_BF,
RX_BF) is not available on port PM7, PM6, PM5, PM4, PM3 and PM2, if using a derivative
without Byteflight (see
Table 0-1
).
–
Do not write MODRR1 and MODRR0 Bit of Module Routing Register (PIM_9DTB128 Block
User Guide), if using a derivative without CAN0 (see
Table 0-1
).
–
Do not write MODRR3 and MODRR2 Bit of Module Routing Register (PIM_9DTB128 Block
User Guide), if using a derivative without CAN4 (see
Table 0-1
).
Pins not available in 80 pin QFP package for
MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, and MC9S12DJ128
Port H
In order to avoid floating nodes the ports should be either configured as outputs by setting the
data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing
a $FF to the pull enable register (PERH at Base+$0264).
–
–
Port J[1:0]
PortJpull-upresistorsareenabledoutofresetonallfourpins(7:6and1:0).Thereforecaremust
be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at
Base+$026C.
–
Port K
Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at
Base+$000C. Therefore care must be taken not to clear this bit.
–
Port M[7:6]
PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
–
Port P6
PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input.
–
Port S[7:4]
PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
–
PAD[15:8] (ATD1 channels)
OutofresettheATD1isdisabledpreventingcurrentflowsinthepins.DonotmodifytheATD1
registers!
Pins not available in 80 pin QFP package for
MC9S12DB128
Port H
In order to avoid floating nodes the ports should be either configured as outputs by setting the
data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing
a $FF to the pull enable register (PERH at Base+$0264).
–
–
Port J[7:6, 1:0]
PortJpull-upresistorsareenabledoutofresetonallfourpins(7:6and1:0).Thereforecaremust
be taken not to disable the pull enables on PJ[7:6, 1:0] by clearing the bits PERJ7, PERJ6,
PERJ1 and PERJ0 at Base+$026C.
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| S12CPUV2 | MC9S12DT128 Device User Guide V02.09 |
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| S12CRGV4 | MC9S12DT128 Device User Guide V02.09 |
| S12CRGV4D | MC9S12DT128 Device User Guide V02.09 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S12BKVD1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Automotive applications |
| S12B-PADSS-1(LF)(SN) | 制造商:JST Manufacturing 功能描述:PAD Series 12 Position 2 mm Pitch Side Entry Shrouded Header Connector |
| S12B-PADSS-1-GW | 制造商:JST Manufacturing 功能描述:12 Position Side Entry Shrouded Header |
| S12B-PASK-2 | 功能描述:CONN HEADR PA 12POS SIDE 2MM TIN RoHS:否 類別:連接器，互連式 >> 矩形- 接頭，公引腳 系列:PA 標(biāo)準(zhǔn)包裝:1 系列:- 觸點(diǎn)類型：:公形引腳 連接器類型:接頭，無罩 位置數(shù):16 加載位置的數(shù)目:全部 間距:0.100"（2.54mm） 行數(shù):1 行間距:- 觸點(diǎn)接合長度:0.230"（5.84mm） 安裝類型:通孔 端子:焊接 緊固型:- 特點(diǎn):- 觸點(diǎn)表面涂層:錫 觸點(diǎn)涂層厚度:100µin（2.54µm） 顏色:黑 包裝:散裝 配套產(chǎn)品:S7049-ND - CONN HEADER FMALE 16POS .1" GOLDS7014-ND - CONN HEADER FEMALE 16POS.1" TINS5647-ND - CONN FMALE 16POS .1" SMD GOLDS5608-ND - CONN FEMALE 16POS .1" SMD TINS5491-ND - CONN FEMALE 16POS .100" R/A GOLDS5452-ND - CONN FEMALE 16POS .100" R/A TINS4546-ND - CONN FMALE 16POS .1" SMD GOLDS4507-ND - CONN FEMALE 16POS .1" SMD TINS4390-ND - CONN FEMALE 16POS .100" R/A GOLDS4351-ND - CONN FEMALE 16POS .100" R/A TIN更多... 其它名稱:S1022-16 |
| S12B-PASK-2(LF)(SN) | 制造商:JST Manufacturing 功能描述:CONN HEADR PA 12POS SIDE 2MM TIN 制造商:JST Manufacturing 功能描述:PA Series 12 Position 2 mm Through Hole Wire to Board Single Row Shrouded Header 制造商:JST Manufacturing 功能描述:12 way side entry PCB header PA 2.0 |
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