參數(shù)資料
型號(hào): S12BKPV1D
廠商: Motorola, Inc.
英文描述: MC9S12DT128 Device User Guide V02.09
中文描述: MC9S12DT128設(shè)備的用戶手冊(cè)V02.09
文件頁數(shù): 61/138頁
文件大?。?/td> 2083K
代理商: S12BKPV1D
MC9S12DT128 Device User Guide — V02.09
61
RESET
TEST
VDDR
N.A.
None
None
None
None
External Reset
Test Input
Voltage Regulator
Enable Input
PLL Loop Filter
Background Debug,
Tag High, Mode Input
Port AD Input,
Analog Inputs,
External Trigger
Input (ATD1)
Port AD Input,
Analog Inputs
(ATD1)
Port AD Input, Analog
Inputs, External
Trigger Input (ATD0)
Port AD Input, Analog
Inputs (ATD0)
Port A I/O,
Multiplexed
Address/Data
Port B I/O,
Multiplexed
Address/Data
VREGEN
VDDX
NA
NA
XFC
VDDPLL
NA
NA
BKGD
TAGHI
MODC
VDDR
Always
Up
Up
PAD[15]
AN1[7]
ETRIG1
VDDA
None
None
PAD[14:8]
AN1[6:0]
VDDA
None
None
PAD[7]
AN0[7]
ETRIG0
VDDA
None
None
PAD[6:0]
AN0[6:0]
VDDA
None
None
PA[7:0]
ADDR[15:8]/
DATA[15:8]
VDDR
PUCR/
PUPAE
Disabled
PB[7:0]
ADDR[7:0]/
DATA[7:0]
VDDR
PUCR/
PUPBE
Disabled
PE7
NOACC
XCLKS
VDDR
PUCR/
PUPEE
Mode
depen-
dant
1
Port E I/O, Access,
Clock Select
PE6
IPIPE1
MODB
VDDR
While RESET pin
low:
Down
Port E I/O, Pipe
Status, Mode Input
Port E I/O, Pipe
Status, Mode Input
Port E I/O, Bus Clock
Output
Port E I/O, Byte
Strobe, Tag Low
Port E I/O, R/W in
expanded modes
Port E Input,
Maskable Interrupt
Port E Input, Non
Maskable Interrupt
PE5
IPIPE0
MODA
VDDR
PE4
ECLK
VDDR
PUCR/
PUPEE
Mode
depen-
dant
1
PE3
LSTRB
TAGLO
VDDR
PE2
R/W
VDDR
PE1
IRQ
VDDR
Up
PE0
XIRQ
VDDR
PH7
KWH7
---
VDDR
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
Disabled Port H I/O, Interrupt
PH6
KWH6
---
VDDR
Disabled Port H I/O, Interrupt
PH5
KWH5
---
VDDR
Disabled Port H I/O, Interrupt
Pin Name
Function 1
Pin Name
Function 2
Pin Name
Function 3
Pin Name
Function 4
Pin Name
Function 5
Powered
by
Internal Pull
Resistor
Description
CTRL
Reset
State
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