參數(shù)資料
型號： S1D2511B01-A0B0
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
中文描述： 偏轉(zhuǎn)處理器多同步監(jiān)測儀
文件頁數(shù)： 25/34頁
文件大?。?/td> 330K
代理商： S1D2511B01-A0B0
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01
25
Figure 8.
PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong
pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump
and the filter (see figure 9 ).
The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the
capacitor, by a current proportionnal to the current in the resistor. Typical thresholds of sawtooth are 1.6V and
6.4V.
Figure 9. Block Diagram
7
PLL1F
1.8K
4.7uF
1uF
INPUT
INTERFACE
COMP1
CHARGE
PUMP
PLL
INHIBITION
VCO
7
8
9
LOCKDET
8
PHASE
ADJUST
OSC
I
2
C
HPOS
Adj.
Low
High
E2
TRAMEXT
HSYNC
H-LOCKCAP
LOCK/UNLOCK
STATUS
TRAMEXT
I
2
C
SMFE
MODE
PLL1F R0
C0
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