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| 型號： | S29AL008D90TAIR10 |
| 廠商： | Spansion Inc. |
| 英文描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 8兆位（1 M中的x 8-Bit/512畝x 16位），3.0伏的CMOS只引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 16/55頁 |
| 文件大?。?/td> | 1723K |
| 代理商： | S29AL008D90TAIR10 |
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June 16, 2005 S29AL008D_00A3
S29AL008D
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Da t a
S h ee t
Figure 4, on page 25 illustrates the algorithm for the erase operation. See Erase
/ Program Operations, on page 42 for parameters, and Figure 18, on page 44 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the address of the sector to be
erased, and the sector erase command. Table 5, on page 25 shows the address
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase.
The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 s begins.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 s, otherwise the last
address and command might not be accepted, and erasure may begin. It is rec-
ommended that processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands
can be assumed to be less than 50 s, the system need not monitor DQ3. Any
command other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data. The system must rewrite the
command sequence and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed
out. (See DQ3: Sector Erase Timer, on page 30.) The time-out begins from the
rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation begins, only the Erase Suspend command is
valid. All other commands are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the operation. The Sector Erase
command sequence should be reinitiated once the device returns to reading array
data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write
Operation Status, on page 27 for information on these status bits.
Figure 4, on page 25 illustrates the algorithm for the erase operation. Refer to
Erase / Program Operations, on page 42 for parameters, and to Figure 18, on
page 44 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase oper-
ation and then read data from, or program data to, any sector not selected for
erasure. This command is valid only during the sector erase operation, including
the 50 s time-out period during the sector erase command sequence. The Erase
Suspend command is ignored if written during the chip erase operation or Em-
bedded Program algorithm. Writing the Erase Suspend command during the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29AL008D90TAIR11 | Ceramic Chip Capacitors / High Voltage; Capacitance [nom]: 20pF; Working Voltage (Vdc)[max]: 1000V; Capacitance Tolerance: +/-20%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Tin (Sn) Plated Nickel Barrier; Body Dimensions: 0.079" x 0.049"; Container: Bulk; Features: High Voltage; Unmarked |
| S29AL008D90TAIR12 | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90TAIR13 | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90TAIR20 | Ceramic Chip Capacitors / High Voltage; Capacitance [nom]: 2.0pF; Working Voltage (Vdc)[max]: 1000V; Capacitance Tolerance: +/-0.25pF; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Tin (Sn) Plated Nickel Barrier; Body Dimensions: 0.079" x 0.049"; Container: Bulk; Features: High Voltage; Unmarked |
| S29AL008D90TAIR21 | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29AL008D90TAIR11 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90TAIR12 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90TAIR13 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90TAIR20 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90TAIR21 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
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