參數(shù)資料
型號： S29CD016G0MFAN003
廠商： SPANSION LLC
元件分類： PROM
英文描述： 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 512K X 32 FLASH 2.7V PROM, 64 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80
文件頁數(shù)： 63/81頁
文件大?。?/td> 1276K
代理商： S29CD016G0MFAN003
64
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
Figure 24.2 Conventional Read Operations Timings
24.3
Burst Mode Read for 32 Mb & 16 Mb
Note
Not 100% tested.
tCE
Outputs
WE#
Addresses
CE#
OE#
High Z
Output Valid
High Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
RY/BY#
RESET#
tDF
tOH
Parameter
Description
Speed Options
Unit
JEDEC
Std.
75 MHz, 0R
32 MHz
66 MHz,
0P
56 MHz,
0M
40 MHz,
OJ
tBACC
Burst Access Time Valid Clock to Output Delay
Max
7.5 FBGA
9 FBGA
9.5 PQFP
10 FBGA
10 PQFP
17
ns
tADVCS ADV# Setup Time to Rising Edge of CLK
Min
5.75
6
tADVCH ADV# Hold Time from Rising Edge of CLK
Min
1.5
2
tADVP
ADV# Pulse Width (32Mb, 75MHz)
Min
12
13
15
22
tDVCH
Valid Data Hold from CLK (See Note)
Min
2
3
tDIND
CLK to Valid IND/WAIT#
Max
7.5 FBGA
9 FBGA
9.5 PQFP
10 FBGA
10 PQFP
17
tINDH
IND/WAIT# Hold from CLK
Min
2
3
CLK to Valid Data Out, Initial Burst Access
Max
48
54
64
67
tCLK
CLK Period
Min
13.
15
18
25
Max
60
tCLKR
CLK Rise Time
Max
3
tCLKF
CLK Fall Time
Max
3
tCKL
CLK Low Time
Min
2
2.5
3
tCLKH
CLK to High Time
Min
2
2.5
3
tCES
CE# Setup Time to Clock
Min
6
tCH
CE# Hold Time
Min
16 Mb =3
32 Mb = 8
tACS
Address Setup Time to CLK
Min
6
tACH
Address Hold Time from ADV# Rising
Edge of CLK while ADV# is Low
Min
5
tOE
Output Enable to Output Valid
Max
20
28
tDF
tOEZ
Output Enable to Output High Z (See Note)
Min
2
3
Max
7.5
10
15
17
tEHQZ
tCEZ
Chip Enable to Output High Z (See Note)
Max
7.5
10
15
17
tWADVH WE hold time after ADV falling edge
Min
0
tWCKS
WE rising edge setup time to clock rising edge
Min
5
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