參數(shù)資料
型號： S29CD016G0MFAN010
廠商： SPANSION LLC
元件分類： PROM
英文描述： 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 512K X 32 FLASH 2.7V PROM, 64 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80
文件頁數(shù)： 37/81頁
文件大?。?/td> 1276K
代理商： S29CD016G0MFAN010
40
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
15. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Table 15.2 on page 52 and Table 15.3 on page 53 define the valid register command sequences.
Writing incorrect address and data values or writing them in the improper sequence resets the device to
reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens first. See AC Characteristics on page 63 for timing
diagrams.
15.1
Reading Array Data in Non-burst Mode
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same exception. See Sector Erase and
Program Suspend Command on page 45 for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or
while in the autoselect mode. See PPB Lock Bit Set Command on page 49.
Resume Command on page 47 for more information on this mode.
15.2
Reading Array Data in Burst Mode
The device is capable of very fast Burst mode read operations. The configuration register sets the read
configuration, burst order, frequency configuration, and burst length.
Upon power on, the device defaults to the asynchronous mode. In this mode, CLK, and ADV# are ignored.
The device operates like a conventional Flash device. Data is available tACC/tCE nanoseconds after address
becomes stable, CE# become asserted. The device enters the burst mode by enabling synchronous burst
reads in the configuration register. The device exits burst mode by disabling synchronous burst reads in the
configuration register. (See Command Definitions on page 40). The RESET# command does not terminate
the Burst mode. System reset (power on reset) terminates the Burst mode.
The device has the regular control pins, i.e. Chip Enable (CE#), Write Enable (WE#), and Output Enable
(OE#) to control normal read and write operations. Moreover, three additional control pins were added to
allow easy interface with minimal glue logic to a wide range of microprocessors / microcontrollers for high
performance Burst read capability. These additional pins are Address Valid (ADV#) and Clock (CLK). CE#,
OE#, and WE# are asynchronous (relative to CLK). The Burst mode read operation is a synchronous
operation tied to the edge of the clock. The microprocessor / microcontroller supplies only the initial address,
all subsequent addresses are automatically generated by the device with a timing defined by the
Configuration Register definition. The Burst read cycle consists of an address phase and a corresponding
data phase.
During the address phase, the Address Valid (ADV#) pin is asserted (taken Low) for one clock period.
Together with the edge of the CLK, the starting burst address is loaded into the internal Burst Address
Counter. The internal Burst Address Counter can be configured to either 2, 4, and 8 double word linear burst,
with or without wrap around. See Initial Access Delay Configuration on page 32.
During the data phase, the first burst data is available after the initial access time delay defined in the
Configuration Register. For subsequent burst data, every rising (or falling) edge of the CLK triggers the output
data with the burst output delay and sequence defined in the Configuration Register.
Table 15.2 on page 52 and Table 15.3 on page 53 show all the commands executed by the device. The
device automatically powers up in the read/reset state. It is not necessary to issue a read/reset command
after power-up or hardware reset.
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