參數(shù)資料
型號： S29CD032G0JFFN002
廠商： SPANSION LLC
元件分類： PROM
英文描述： 1M X 32 FLASH 2.7V PROM, 67 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80
文件頁數(shù)： 41/81頁
文件大小： 1276K
代理商： S29CD032G0JFFN002
44
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
15.7.4
Unlock Bypass CFI Command
The Unlock Bypass CFI command is available for PROM programmers and target systems to read the CFI
codes while in Unlock Bypass mode. See Common Flash Interface (CFI) Command on page 47 for specific
CFI codes.
To return back to standard read operations, the Unlock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.
15.7.5
Unlock Bypass Reset Command
The Unlock Bypass Reset command places the device in standard read/reset operating mode. Once
executed, normal read operations and user command sequences are available for execution.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.
15.8
Chip Erase Command
The Chip Erase command is used to erase the entire flash memory contents of the chip by issuing a single
command. Chip erase is a six-bus cycle operation. There are two unlock write cycles, followed by writing the
erase set-up command. Two more unlock write cycles are followed by the chip erase command. Chip erase
does not erase protected sectors.
The chip erase operation initiates the Embedded Erase algorithm, which automatically preprograms and
verifies the entire memory to an all zero pattern prior to electrical erase. The system is not required to provide
any controls or timings during these operations. Note that a hardware reset immediately terminates the
programming operation. The command sequence should be reinitiated once that bank returns to reading
array data, to ensure data integrity.
The Embedded Erase algorithm erase begins on the rising edge of the last WE# or CE# pulse (whichever
occurs first) in the command sequence. The status of the erase operation is determined three ways:
Data# polling of the DQ7 pin (See DQ7: Data# Polling on page 54)
Checking the status of the toggle bit DQ6 (See DQ6: Toggle Bit I on page 56)
Checking the status of the RY/BY# pin (See RY/BY#: Ready/Busy# on page 54)
Once erasure begins, only the Erase Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device returns to reading array data, and addresses
are no longer latched. Note that an address change is required to begin read valid array data.
Figure 15.2 on page 46 illustrates the Embedded Erase Algorithm. See Erase/Program Operations
on page 68 for parameters, and Figure 24.8 on page 69 and Figure 24.9 on page 69 for timing diagrams.
15.9
Sector Erase Command
The Sector Erase command is used to erase individual sectors or the entire flash memory contents. Sector
erase is a six-bus cycle operation. There are two unlock write cycles, followed by writing the erase set-up
command. Two more unlock write cycles are then followed by the erase command (30h). The sector address
(any address location within the desired sector) is latched on the falling edge of WE# or CE# (whichever
occurs last) while the command (30h) is latched on the rising edge of WE# or CE# (whichever occurs first).
Specifying multiple sectors for erase is accomplished by writing the six bus cycle operation, as described
above, and then following it by additional writes of only the last cycle of the Sector Erase command to
addresses or other sectors to be erased. The time between Sector Erase command writes must be less than
80 s, otherwise the command is rejected. It is recommended that processor interrupts be disabled during
this time to guarantee this critical timing condition. The interrupts can be re-enabled after the last Sector
Erase command is written. A time-out of 80 s from the rising edge of the last WE# (or CE#) initiates the
execution of the Sector Erase command(s). If another falling edge of the WE# (or CE#) occurs within the 80
s time-out window, the timer is reset. Once the 80 s window times out and erasure begins, only the Erase
Suspend command is recognized (See Sector Erase and Program Suspend Command on page 45 and
Sector Erase and Program Resume Command on page 47). If that occurs, the sector erase command
sequence should be reinitiated once that bank returns to reading array data, to ensure data integrity. Loading
the sector erase registers may be done in any sequence and with any number of sectors.
相關PDF資料
PDF描述
S29CD032G0RFFN003 1M X 32 FLASH 2.7V PROM, 48 ns, PBGA80
S29CD032G0RQFI012 1M X 32 FLASH 2.7V PROM, 48 ns, PQFP80
S29CL032J0JFAM020 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80
S29CL032J0JFFM020 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80
S29CL032J0RFAM012 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80
相關代理商/技術參數(shù)
參數(shù)描述
S29CD032G0JQAA000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD032G0JQAA002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD032G0JQAA010 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD032G0JQAA012 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
S29CD032G0JQAA100 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O
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