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參數(shù)資料
| 型號(hào)： | S29GL032M10TAIR40 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | CAP 1.0UF 500V 10% X7R RAD-.475 .570X.500 CONF BULK |
| 中文描述： | 2M X 16 FLASH 3V PROM, 100 ns, PDSO48 |
| 封裝： | MO-142EC, TSOP-48 |
| 文件頁(yè)數(shù)： | 36/116頁(yè) |
| 文件大小： | 6024K |
| 代理商： | S29GL032M10TAIR40 |
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24
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
Data
Sheet
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO
± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held
at VIH, but not within VIO ± 0.3 V, the device is in the standby mode, but the standby current is
greater. The device requires standard access time (tCE) for read access when the device is in ei-
ther of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.
See DC Characteristics for the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always
available to the system. See DC Characteristics for the automatic sleep mode current
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When
the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all output pins, and ignores all read/write commands for the du-
ration of the RESET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the
device draws CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS±0.3 V, the
standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset
the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
See AC Characteristics for RESET# parameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in
the high impedance state.
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