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參數(shù)資料
| 型號(hào)： | S29GL064A10BAIW12 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 3V PROM, 100 ns, PBGA64 |
| 封裝： | FBGA-64 |
| 文件頁(yè)數(shù)： | 62/97頁(yè) |
| 文件大?。?/td> | 3490K |
| 代理商： | S29GL064A10BAIW12 |
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January 11, 2006 S29GL-A_00_A5
S29GL-A MirrorBit Flash Family
63
Pr el im i n a r y
Write Operation Status
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 32 on page 68 and the follow-
ing subsections describe the function of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase operation is complete or in
progress. The device also provides a hardware-based output signal, RY/BY#, to
determine whether an Embedded Program or Erase operation is in progress or is
completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether the device
is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE#
pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 s, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must pro-
vide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 s, then the
device returns to the read mode. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the system reads DQ7 at an
address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as-
serted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device completed the program or
erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may be
still invalid. Valid data on DQ0–DQ7 appears on successive read cycles.
Table 32 on page 68 shows the outputs for Data# Polling on DQ7. Figure 7, on
page 64 shows the Data# Polling algorithm. Figure 19, on page 80 shows the
Data# Polling timing diagram.
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