參數(shù)資料
型號: S29PL032J65BFI150
廠商: SPANSION LLC
元件分類: PROM
英文描述: 2M X 16 FLASH 3V PROM, 65 ns, PBGA56
封裝: 7 X 9 MM, LEAD FREE, FBGA-56
文件頁數(shù): 11/94頁
文件大?。?/td> 949K
代理商: S29PL032J65BFI150
July 29, 2005 S29PL-J_00_A8
S29PL-J
17
Advance
Information
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any ad-
dressable memory location. The register is a latch used to store the commands, along with the
address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the inputs and control levels they require, and
the resulting output. The following subsections describe each of these operations in further
detail.
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the High
2. WP#/ACC must be high when writing to upper two and lower two sectors.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appropriate CE# pins
(For PL129J - CE1#/CE2# pins) to VIL. In PL129J, CE1# and CE2# are the power control and
select the lower (CE1#) or upper (CE2#) halves of the device. CE# is the power control. OE# is
the output control and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hard-
ware reset. This ensures that no spurious alteration of the memory content occurs during the
power transition. No command is necessary in this mode to obtain array data. Standard micro-
processor read cycles that assert valid addresses on the device address inputs produce valid data
on the device data outputs. Each bank remains enabled for read access until the command reg-
ister contents are altered.
Table 1 PL127J Device Bus Operations
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(Amax–A0)
DQ15–
DQ0
Read
LL
H
X
AIN
DOUT
Write
LH
L
H
DIN
Standby
VIO±0.3 V
X
VIO ±0.3 V
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
Temporary Sector Unprotect
(High Voltage)
XX
X
VID
XAIN
DIN
Table 2 PL129J Device Bus Operations
Operation
CE1#
CE2#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A21–A0)
DQ15–
DQ0
Read
L
H
LH
H
X
AIN
DOUT
HL
Write
L
H
HL
H
X
AIN
DIN
HL
Standby
VIO±
0.3 V
VIO ±
0.3 V
XX
VIO ±
0.3 V
XX
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
Temporary Sector Unprotect
(High Voltage)
XX
X
VID
XAIN
DIN
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