參數(shù)資料
型號(hào)： S29WS128J0PBAW002
廠商： SPANSION LLC
元件分類： PROM
英文描述： 8M X 16 FLASH 1.8V PROM, 55 ns, PBGA84
封裝： 8 X 11.60 MM, FBGA-84
文件頁(yè)數(shù)： 7/97頁(yè)
文件大?。?/td> 2421K
代理商： S29WS128J0PBAW002
May 11, 2006 S29WS-J_00_A6
S29WS128J/064J
15
D a ta
Sh eet
Prior to entering burst mode, the system should determine how many wait states are desired for
the initial word (tIACC) of each burst access, what mode of burst operation is desired, which edge
of the clock will be the active clock edge, and how the RDY signal will transition with valid data.
The system would then write the configuration register command sequence. See “Set Configura-
page 46 for further details.
Once the system has written the “Set Configuration Register” command sequence, the device is
enabled for synchronous reads only.
The initial word is output tIACC after the active edge of the first CLK cycle. Subsequent words are
output tBACC after the active edge of each successive clock cycle, which automatically increments
the internal address counter. Note that the device has a fixed internal address boundary that oc-
curs every 64 words, starting at address 00003Fh.
During the time the device is outputting data at this fixed internal address boundary (address
00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency (WS128J/064J model numbers 00 and
01) or a three cycle latency (WS128J model numbers 10 and 11) occurs before data appears for
the next address (address 000040h, 000080h, 0000C0h, etc.).
Additionally, when the device is read from an odd address, one wait state is inserted when the
address pointer crosses the first boundary that occurs every 16 words. For instance, if the device
is read from 000011h, 000013h, … ,00001Fh (odd), one wait state is inserted before the data of
000020h is output. This wait is inserted only at the boundary of the first 16 words. Then, if the
device is read from the odd address within the last 16 words of 64 word boundary (address
000031h,000033h, … , 00003Fh), a three-cycle latency occurs before data appears for the next
address (address 000040h). During the boundary crossing condition, the system must assert an
additional wait state for WS128J model numbers 10 and 11.
The RDY output indicates this condition to the system by pulsing deactive (low). See Figure 35,
The device will continue to output sequential burst data, wrapping around to address 000000h
after it reaches the highest addressable memory location, until the system drives CE# high, RE-
SET# low, or AVD# low in conjunction with a new address. See Table 1, “Device Bus Operations,”
If the host system crosses the bank boundary while reading in burst mode, and the device is not
programming or erasing, a two-cycle latency will occur as described above in the subsequent
bank. If the host system crosses the bank boundary while the device is programming or erasing,
the device will provide read status information. The clock will be ignored. After the host has com-
pleted status reads, or the device has completed the program or erase operation, the host can
restart a burst operation using a new address and AVD# pulse.
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three burst read modes are of the linear wrap around design, in which a fixed num-
ber of words are read from consecutive addresses. In each of these modes, the burst addresses
read are determined by the group within which the starting address falls. The groups are sized
according to the number of words read in a single burst sequence for a given mode (see Table 2.)
Table 2. Burst Address Groups
Mode
Group Size
Group Address Ranges
8-word
8 words
0-7h, 8-Fh, 10-17h,...
16-word
16 words
0-Fh, 10-1Fh, 20-2Fh,...
32-word
32 words
00-1Fh, 20-3Fh, 40-5Fh,...
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