參數(shù)資料
型號(hào)： S29WS128J0PBAW002
廠商： SPANSION LLC
元件分類： PROM
英文描述： 8M X 16 FLASH 1.8V PROM, 55 ns, PBGA84
封裝： 8 X 11.60 MM, FBGA-84
文件頁數(shù)： 90/97頁
文件大?。?/td> 2421K
代理商： S29WS128J0PBAW002
90
S29WS128J/064J
S29WS-J_00_A6 May 11, 2006
Dat a
S h ee t
Notes:
1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing
a bank in the process of performing an erase or program.
Figure 36. Latency with Boundary Crossing into Program/Erase Bank
CLK
Address (hex)
C60
C61
C62
C63
D60
D61
D62
D63
Read Status
(stays high)
AVD#
RDY(1)
Data
OE#,
CE#
(stays low)
Address boundary occurs every 64 words, beginning at address
00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
3C
3D
3E
3F
latency
RDY(2)
latency
tRACC
C64
C65
C66
40
41
42
D63
Invalid
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