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| 型號： | S29WS128J0PBFW002 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 55 ns, PBGA84 |
| 封裝： | 8 X 11.60 MM, LEAD FREE, FBGA-84 |
| 文件頁數(shù)： | 64/97頁 |
| 文件大小： | 2421K |
| 代理商： | S29WS128J0PBFW002 |
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May 11, 2006 S29WS-J_00_A6
S29WS128J/064J
67
D a ta
Sh eet
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was
previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this
condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 pro-
duces a “1.”
Under both these conditions, the system must write the reset command to return to the read
mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program
mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether
or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire time-out also applies after each additional
sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.”
If the time between additional sector erase commands from the system can be assumed to be
less than 50 s, the system need not monitor DQ3. See also Sector Erase Command Sequence
After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and
then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands
(except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device
will accept additional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status check, the last command might not have
been accepted.
Table 20 shows the status of DQ3 relative to the other status bits.
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
4. The system may read either asynchronously or synchronously (burst) while in erase suspend.
5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This
is available in the Asynchronous mode only.
6. When the device is set to Asynchronous mode, these status flags should be read by CE# toggle.
Table 20. Write Operation Status
Status
DQ7
DQ6
DQ5
DQ3
DQ2
RDY (Note 5)
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Erase
Suspend
Mode
Erase-Suspend-
Read (Note 4)
Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
High Impedance
Non-Erase Suspended
Sector
Data
High Impedance
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
0
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