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Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
MC9S12HZ256 Data Sheet, Rev. 2.05
104
Freescale Semiconductor
3.3.2.7
EEPROM Command Register (ECMD)
The ECMD register defines the EEPROM commands.
CMDB6, CMDB5, CMDB2, and CMDB0 bits are readable and writable during a command sequence
while bits 7, 4, 3, and 1 read 0 and are not writable.
4
ACCERR
EEPROM Access Error — The ACCERR ag indicates an illegal access to the selected EEPROM array
an illegal command (illegal combination of the CMDBx bits in the ECMD register) or the execution of a CPU
STOP instruction while a command is executing (CCIF = 0). The ACCERR ag is cleared by writing a 1 to
ACCERR. Writing a 0 to the ACCERR ag has no effect on ACCERR. While ACCERR is set, it is not possible to
launch another command in the EEPROM.
0 No failure
1 Access error has occurred
2
BLANK
Array Has Been Veried as Erased — The BLANK ag indicates that an erase verify command has checked
the EEPROM array and found it to be erased. The BLANK ag is cleared by hardware when CBEIF is cleared
as part of a new valid command sequence. Writing to the BLANK ag has no effect on BLANK.
0 If an erase verify command has been requested and the CCIF ag is set, then a 0 in BLANK indicates array
is not erased
1 EEPROM array veries as erased
1
FAIL
Flag Indicating a Failed EEPROM Operation — The FAIL ag will set if the erase verify operation fails
(EEPROM block veried as not erased). The FAIL ag is cleared writing a 1 to FAIL. Writing a 0 to the FAIL ag
has no effect on FAIL.
0 EEPROM operation completed without error
1 EEPROM operation failed
0
DONE
Flag Indicating a Completed EEPROM Operation
0 EEPROM operation is active (program, erase, erase verify)
1 EEPROM operation not active
76543210
R0
CMDB6
CMDB5
00
CMDB2
0
CMDB0
W
Reset
0
00000
= Unimplemented or Reserved
Figure 3-11. EEPROM Command Register (ECMD)
Table 3-8. ECMD Field Descriptions
Field
Description
6, 5, 2, 0
CMDB[6:5]
CMDB2
CMDB0
EEPROM Command — Valid EEPROM commands are shown in
Table 3-9. Any other command written than
those mentioned in
Table 3-9 sets the ACCERR bit in the ESTAT register.
Table 3-7. ESTAT Field Descriptions (continued)
Field
Description