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參數(shù)資料
| 型號： | S5L9284D01-Q0R0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | IC, 10/100BASE-TX DUAL-PORT DIGI-PHY TRANSCEIVER, QFP14 |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 350K |
| 代理商： | S5L9284D01-Q0R0 |
DIGITAL SIGNAL PROCESSOR
S5L9284D
21
CLV SERVO BLOCK
The CNTL-C register is selected to control the CLV (Constant Linear Velocity) servo by the data input from micom.
In the CNTL-C register, the CLV servo action mode is appointed by the data input from micom to control the spindle
motor. In case of a double-speed setting, the CNTL-C register has to be selected after the CNTL-D register sets, so
that it is able to detect / (Pw
≥
64) signal from the /ISTAT terminal.
Forward Mode
The status of the related output terminals are as follows.
Reverse Mode
The status of the related output terminals are as follows.
Speed-Mode
The speed-mode is the mode for the rough control of a spindle motor when a track is jumping or when an EFM
phase is unlocked. If a period of VCO is
“
T
”
, the pulse width of frame sync is
“
22T
”
. In case that the signal detected
from an EFM signal exceeds
“
22T
”
by noise on the disc.... etc., it must be removed. If not, the right frame sync
can
’
t be detected. In this case, the pulse width of the EFM signal is detected by peak and bottom hold clock. The
peak hold clock is XTFR/2 or XTR/4, and the bottom hold clock is XTFR/16 or XTFR/32. The detected value is used
for the synchronized frame signal. If a synchronized frame signal is less than 21T, the SMDP terminal outputs
“
L
”
.
When it is equal to 22T, it outputs
“
HiZ
”
, and when it is more than 23T, it outputs
“
H
”
. If the gain signal of the CNTL-
W register is
“
L
”
, the output of SMDP terminal is reduced up to - 12 dB. If it is
“
H
”
, there is no reduction.
Hi-Speed-Mode
The rough servo mode, which moves 20,000 tracks in high speed, acts between the inner and outer peripheries of
the CD. The track
’
s mirror domain ( where there are no pits ) is duplicated with 20 kHz signals to the EFM. In this
case, the servo action is unstable, because, the peak value of the mirror signal is longer than the original frame
signal, which is detected. In Hspeed mode, by using the 8.4672/256 MHz signal against peak hold, and the XTFR/
16 or XTFR/32 signal against bottom hold, the mirror is removed , and the Hspeed action becomes stable . The
output conditions in Hspeed mode are: SMSD is
“
Hi-Z
”
,
“
SMEF
”
is
“
L
”
, and SMON is
“
H
”
.
Phase-Mode
The phase-mode is the mode to control the EFM phase. Phase difference between PBFR/4 and XTFR/4 is
detected when NCLV of CNTL-Z is
“
L
”
and the difference is output to the SMDP terminal. If a cycle of VCO/2 signal
is put as
“
T
”
and it is put as
“
/WP
”
during an
“
H
”
period of PBFR, it outputs
“
H
”
to the SMSD terminal from the
falling edge of PBFR to the (/WP-278T) X 32, and then, outputs
“
L
”
to the falling edge of the next.
SMDP
SMSD
SMEF
SMON
H
Hi-Z
L
H
SMDP
SMSD
SMEF
SMON
L
Hi-Z
L
H
SMDP
SMSD
SMEF
SMON
Hi-Z
L
H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5L9284D | DIGITAL SIGNAL PROCESSOR |
| S5L9286F02 | DIGITAL SIGNAL PROCESSOR |
| S5L9286F02-T0R0 | DIGITAL SIGNAL PROCESSOR |
| S5L9286F01-Q0R0 | IC, TRANS, PHY, DUAL, 10/100BASE-TX |
| S5L9286 | DIGITAL SIGNAL PROCESSOR FOR CDP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5L9286 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR FOR CDP |
| S5L9286F01-Q0R0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR FOR CDP |
| S5L9286F02 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR |
| S5L9286F02-T0R0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR FOR DISCMAN |
| S5L9290X | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:signal processing LSI for the CD |
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