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參數(shù)資料
| 型號(hào)： | S5L9284D01-Q0R0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | IC, 10/100BASE-TX DUAL-PORT DIGI-PHY TRANSCEIVER, QFP14 |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 350K |
| 代理商： | S5L9284D01-Q0R0 |
S5L9284D
DIGITAL SIGNAL PROCESSOR
4
PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
AV
DD1
Analog supply voltage 1
2
DPDO
O
Charge pump output for master PLL
3
DPFIN
I
Filter input for master PLL
4
DPFOUT
O
Filter output for master PLL
5
CNTVOL
I
VCO control voltage for master PLL
6
AV
SS1
Analog ground 1
7
DATX
O
Digital audio output
8
XIN
I
X-tal oscillator input (16.9344MHz / 33.8688MHz)
9
XOUT
O
X-tal oscillator output
10
WDCH1
O
Word clock of 48 bits/slot
11
LRCH1
O
Channel clock of 48 bits/slot
12
SADT1
O
Serial audio data output with 48 bits/slot
13
DV
SS1
Digital ground 1
14
BCK1
O
Serial audio data bit clock for 48 bits/slot
15
C2PO
O
C2 pointer for serial audio data
16
TIM2
O
Normal or double speed control output pin
17
/BCK1
O
Inverted clock of BCK1
18
/BCK2
O
Inverted clock of BCK2
19
BCK2
O
Serial audio data bit clock for 64 bits/slot
20
LRCH2
O
Channel clock for 64 bits/slot
21
SADT2
O
Serial audio data output with 64 bits/slot
22
TEST0
I
Test input pin (
“
L
”
: normal,
“
H
”
: test)
23
WDCH2
O
Word clock of 64 bit/slot
24
EMPH
O
Emphasis/Non-emphasis output (
“
H
”
: Emphasis)
25
LKFS
O
The lock status output of frame sync
26
S0S1
O
Output of subcode sync signal (S0 + S1)
27
RESET
I
System reset at Low
28
SQEN
I
SQCK control input (
“
L
”
: internal clock,
“
H
”
: external clock)
29
SQCK
I/O
Subcode-Q data bit clock
30
SQDT
O
Subcode-Q data serial output
31
SQOK
O
The CRC check result signal output of subcode-Q
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