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S5N8947 (ADSL/Cable Modem MCU)
ELECTRONICS
MagIC Team
Page : 20
SAMSUNG ELECTRONICS
6. H
ARDWARE
S
TRUCTURE
6.1. System Manager
6.1.3. Overview
The S5N8947 microcontroller’s System Manager has the following functions.
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To arbitrate system bus access requests from several master blocks, based on fixed priorities.
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To provide the required memory control signals for external memory accesses. For example, if a
master block such as the DMA controller or the CPU generates an address which corresponds to a
DRAM bank, the System Manager’s DRAM controller generates the required normal/EDO or
SDRAM access signals. The interface signals for normal/EDO or SDRAM can be switched by
SYSCFG[31].
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To provide the required signals for bus traffic between the S5N8947 and ROM/SRAM and the
external I/O banks.
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To compensate for differences in bus width for data flowing between the external memory bus and the
internal data bus.
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To support both little and big endian for external memory or I/O devices. Internal registers, however,
operate under big-endian mode.
Note
: By generating an external bus request (ExtMREQ), an external device can access the S5N8947’s
external memory. The S5N8947 can access slow external devices using a nDTACK signal. The DTACK
signal, which is generated by the external device, extends the duration of the CPU’s memory access cycle
beyond its programmable value.
6.1.4. System Manager Registers
To control external memory operations, the System Manager uses a dedicated set of special registers.
By programming the values in the System Manager special registers, you can specify such things as :
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Memory type
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External bus width access cycle
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Control signal timing (RAS and CAS, for example)
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Memory bank locations
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Size of each memory bank to be used for arbitrary address spacing
The System Manager uses special register setting to control the generation and processing of the
control signals, addresses, and data that are required by external devices in a standard system
configuration. Special registers are also used to control access to ROM/SRAM/Flash banks, up to four
DRAM banks and four external I/O banks, and a special register mapping area.