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參數資料
| 型號： | S5N8950 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | G.dmt ADSL Transceiver for CO and CPE |
| 中文描述： | G.dmt寬帶收發(fā)器對CO和CPE |
| 文件頁數： | 7/19頁 |
| 文件大?。?/td> | 203K |
| 代理商： | S5N8950 |
S5N8950
G.dmt ADSL Transceiver for CO and CPE
CONFIDENTIAL
Preliminary Information ( Rev 1.2 )
A_AD_DATA[6:0]
A_AD_REF_CLK
A_AD_AUX_CLK
A_DA_DATA[6:0]
A_DA_REF_CLK
A_DA_AUX_CLK
A_SDI
A_AND
A_BUSY
A_SCLK
A_SDO
A_SEN
A_PME
A_TX_PWR
A_RX_PWR
A_RSTN
I
I
I
PHICD
PHICD
PHICD
PHOB2
PHOB2
PHOB2
PHICU
PHICD
PHICD
PHOB2
PHOB2
PHOB2
PHICD
PHOB2
PHOB2
PHOB2
ADC data for 2 phase.
ADC data reference clock for DMT b2b test
ADC data strobe clock for DMT b2b test
DAC data for 2 phase
DAC data reference clock
DAC data strobe clock
AFE serial input data
Audible noise detection (active high)
AFE busy ( active high)
AFE serial clock
AFE serial output data
AFE serial enable ( active low )
AFE power management enable
TX line driver power enable ( active high )
RX line driver power enable ( active high )
AFE reset ( active low )
O
O
O
I
I
I
O
O
O
O
O
O
O
AFE
interface
B_RSTN
B_GP_OUT[1:0]
I
PHIS
PHOB2
System reset ( active low )
General purpose output
TeakLite boot mode selection
[0] = simple reset
[1] = boot from Host CPU ( normal mode )
[2] = boot from JTAG ( emulation mode )
[3] = self-booting ( test mode )
Test Mode Enable
(DSP view, Scan Test, Memory BIST, PLL Test)
[0] Normal, [1] Test Mode
NAND tree test mode
[0] Normal, [1] NAND tree test mode
ATM Network Timing Reference
external clock
misc. clock for BIRA test
XTAL input for clock.
XTAL output for clock.
Internal PLL pump out connected to filter.
O
B_BMODE[1:0]
I
PHIC
B_TMODE
I
PHIC
B_NMODE
I
PHIC
B_NTR
B_EXT_CLK
B_MSC_CLK
P_XTAL_IN
P_XTAL_OUT
P_PLL_FILTER
B
I
I
I
O
O
PHTBCT4
PHIC
PHIC
PHSOSCM26
POAR50_ABB
Board /
PLL
interface
T_MS
T_CLK
T_DI
T_DO
T_INTP
I
I
I
PHTICD
PHTICD
PHTICD
PHTOT4
PHOB4
TeakLite JTAG test mode select
TeakLite JTAG test clock
TeakLite JTAG test input data
TeakLite JTAG test output data
TeakLite TJAM interrupt to host
OZ
O
TeakLite
Interface
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