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S5N8950
G.dmt ADSL Transceiver for CO and CPE
CONFIDENTIAL
Preliminary Information ( Rev 1.2 )
Pad
I/O
I
I
OZ
O
O
I
I
I
I
I
B
Description
PHTIC
PHTICD
PHTOT4
PHOB4
PHOB2
PHIC
PHICD
PHICU
PHICD
PHIS
PHTBCT4
5V tolerant for 3.3 V interface LVCMOS level input buffer
5V tolerant for 3.3 V interface LVCMOS level input buffer with pull-down register.
5V tolerant for 3.3 V interface tri-state output buffer driving 4 mA
3.3 V LVCMOS normal output buffer driving 4 mA
3.3 V LVCMOS normal output buffer driving 2 mA
3.3 V interface LVCMOS level input buffer
3.3 V interface LVCMOS level input buffer with pull-down register.
3.3 V interface LVCMOS level input buffer with pull-up resister
3.3 V interface LVCMOS level input buffer with pull-down resister
3.3 V interface LVCMOS Schmitt-trigger level input buffer
3.3 V interface 5 V tolerant LVCMOS level tri-state bi-directional buffer
driving 4 mA
3.3 V interface 5 V tolerant LVCMOS level tri-state bi-directional buffer
driving 6 mA medium slew rate control
3.3 V interface 5 V tolerant LVCMOS level tri-state bi-directional buffer
driving 6 mA medium slew rate control with pull-down register.
Analog normal output pad for 1.8 V interface
with resister 50 Ohm and separated bulk bias
Oscillator cell with enable and feedback resistor.
Power, 1.8 V total with separate bulk bias
Ground, 1.8 V total with separate bulk bias
Ground, 1.8 V bulk bias
VDD for 1.8 V internal power
VSS for 1.8 V internal power
VDD for 3.3 V output driver power
VSS for 3.3 V output driver power
VDD for 3.3 V pre- driver power
VSS for 3.3 V pre- driver power
VDD for 3.3 V output driver and pre- driver power
VSS for 3.3 V output driver and pre- driver power
PHTBCT6SM
B
PHTBCDT6SM
B
POAR50_ABB
O
PHSOSCM26
VDD1T_ABB
VSS1T_ABB
VBB1_ABB
VDD1I
VSS1I
VDD3O
VSS3O
VDD3P
VSS3P
VDD3OP
VSS3OP
I/O
I
I
I
I
I
I
I
I
I
I
I
Table 2: Pad description