參數(shù)資料
型號: S71GL128NC0BAWAZ0
廠商: SPANSION LLC
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA84
封裝: 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE COMPLIANT, FBGA-84
文件頁數(shù): 4/122頁
文件大小: 1764K
代理商: S71GL128NC0BAWAZ0
December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
101
Ad vance
Info rmat i o n
AC Characteristics
Alternate CE# Controlled Erase and Program Operations-
S29GL128N, S29GL256N, S29GL512N
Notes:
1. Not 100% tested.
2. See the “AC Characteristics” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 90 ns, 100ns, and 110 ns speed options are tested with VIO = VCC
= 3 V. AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
Parameter
Speed Options
JEDEC
Std.
Description
90
100
110
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
90
100
110
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
TASO
Address Setup Time to OE# low during
toggle bit polling
Min
15
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tAHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
tDVEH
tDS
Data Setup Time
Min
45
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tCEPH CE# High during toggle bit polling
Min
20
ns
tOEPH OE# High during toggle bit polling
Min
20
ns
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
35
ns
tEHEL
tCPH CE# Pulse Width High
Min
30
ns
tWHWH1 tWHWH1
Write Buffer Program Operation (Notes 2,
3)
Typ
240
s
Effective Write Buffer
Program Operation (Notes
2, 4)
Per Word
Typ
15
s
Effective Accelerated Write
Buffer Program Operation
(Notes 2, 4)
Per Word
Typ
13.5
s
Program Operation (Note 2)
Word
Typ
60
s
Accelerated Programming
Operation (Note 2)
Word
Typ
54
s
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Typ
0.5
sec
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