參數(shù)資料
型號： S80C32-44:RD
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 44 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 146/152頁
文件大小： 2528K
91
8151H–AVR–02/11
ATmega128A
cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the
interrupt is re-enabled.
Note:
1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
13.1.2
EICRB - External Interrupt Control Register B
Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in Table 13-3. The value on the INT7:4 pins are sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled. If low level interrupt is selected, the low level must be held until the comple-
tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered
interrupt will generate an interrupt request as long as the pin is held low.
Note:
1. n = 7, 6, 5 or 4.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Table 13-1.
Interrupt Sense Control
ISCn1
ISCn0
Description
0
The low level of INTn generates an interrupt request.
01
Reserved
1
0
The falling edge of INTn generates asynchronously an interrupt request.
1
The rising edge of INTn generates asynchronously an interrupt request.
Table 13-2.
Asynchronous External Interrupt Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
tINT
Minimum pulse width for asynchronous
external interrupt
50
ns
Bit
76543210
ISC71
ISC70
ISC61
ISC60
ISC51
ISC50
ISC41
ISC40
EICRB
Read/Write
R/W
Initial Value
00000000
Table 13-3.
Interrupt Sense Control
ISCn1
ISCn0
Description
0
The low level of INTn generates an interrupt request.
0
1
Any logical change on INTn generates an interrupt request
1
0
The falling edge between two samples of INTn generates an interrupt request.
1
The rising edge between two samples of INTn generates an interrupt request.
相關(guān)PDF資料
PDF描述
MQ80C52XXX-36/883 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
S80C32-L16D 8-BIT, 16 MHz, MICROCONTROLLER, PQCC44
MP80C51C-36D 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PDIP40
MR80C52EXXX-16SHXXX:R 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
MD83C154DCXXX-25P883D 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S80C32-L16 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
S80C32-L16R 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
S80C376CB8 WAF 制造商:Intel 功能描述:
S80C42 制造商:Intel 功能描述:
S80C51 WAF 制造商:Intel 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*