參數(shù)資料
型號： S80C32-44:RD
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 44 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 21/152頁
文件大?。?/td> 2528K
117
2486AA–AVR–02/2013
ATmega8(L)
Asynchronous
Operation of the
Timer/Counter
Asynchronous Status
Register – ASSR
Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clk
I/O. When AS2 is
written to one, Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscil-
lator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2, and
TCCR2 might be corrupted.
Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.
When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.
Bit 1 – OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set.
When OCR2 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value.
Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set.
When TCCR2 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2,
the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary stor-
age register is read.
Asynchronous
Operation of
Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A
safe procedure for switching clock source is:
1.
Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2
2.
Select clock source by setting AS2 as appropriate
3.
Write new values to TCNT2, OCR2, and TCCR2
4.
To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB
5.
Clear the Timer/Counter2 Interrupt Flags
6.
Enable interrupts, if needed
The Oscillator is optimized for use with a 32.768kHz watch crystal. Applying an external
clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main
clock frequency must be more than four times the Oscillator frequency
When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a
temporary register, and latched after two positive edges on TOSC1. The user should not
Bit
765
43
2
1
0
–
AS2
TCN2UB
OCR2UB
TCR2UB
ASSR
Read/Write
RRRR
R/W
R
Initial Value
0
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