116
32000D–04/2011
AVR32
st.b
C
Rp++, Rs
Store with post-increment.
*(Rp++)
← Rs[7:0]
1
C
--Rp, Rs
Store with pre-decrement.
*(--Rp)
← Rs[7:0]
1
C
Rp[disp], Rs
Store byte with displacement.
*(Rp+ZE(disp3))
← Rs[7:0]
1
E
Rp[disp], Rs
*(Rp+SE(disp16))
← Rs[7:0]
1
E
Rb[Ri<<sa], Rs
Indexed Store byte.
*(Rb+(Ri << sa2))
← Rs[7:0]
1
st.b{cond4}
E
Rp[disp], Rs
Store byte with displacement if condition
satisfied.
if {cond4}
*(Rp+SE(disp9))
← Rs[7:0]
2
st.d
C
Rp++, Rs
Store with post-increment.
*(Rp++)
← (Rs+1:Rs)
1
C
--Rp, Rs
Store with pre-decrement.
*(--Rp)
← (Rs+1:Rs)
1
C
Rp, Rs
Store doubleword
*(Rp)
← (Rs+1:Rs)
1
E
Rp[disp], Rs
Store double with displacement
*(Rp+SE(disp16))
← (Rs+1:Rs)
1
E
Rb[Ri<<sa], Rs
Indexed Store double.
*(Rb+(Ri << sa2))
← (Rs+1:Rs)
1
st.h
C
Rp++, Rs
Store with post-increment.
*(Rp++)
← Rs[15:0]
1
C
--Rp, Rs
Store with pre-decrement.
*(--Rp)
← Rs[15:0]
1
C
Rp[disp], Rs
Store halfword with displacement.
*(Rp+(ZE(disp3)<<1))
← Rs[15:0]
1
E
Rp[disp], Rs
*(Rp+(SE(disp16)))
← Rs[15:0]
1
E
Rb[Ri<<sa], Rs
Indexed Store halfword.
*(Rb+(Ri << sa2))
← Rs[15:0]
1
st.h{cond4}
E
Rp[disp], Rs
Store halfword with displacement if
condition satisfied.
if {cond4}
*(Rp+SE(disp9<<1))
← Rs[15:0]
2
st.w
C
Rp++, Rs
Store with post-increment.
*(Rp++)
← Rs
1
C
--Rp, Rs
Store with pre-decrement.
*(--Rp)
← Rs
1
C
Rp[disp], Rs
Store word with displacement.
*(Rp+(ZE(disp4)<<2))
← Rs
1
E
Rp[disp], Rs
*(Rp+(SE(disp16)))
← Rs
1
E
Rb[Ri<<sa], Rs
Indexed Store word.
*(Rb+(Ri << sa2))
← Rs
1
st.w{cond4}
E
Rp[disp], Rs
Store word with displacement if condition
satisfied.
if {cond4}
*(Rp+ZE(disp9<<2))
← Rs
2
stcond
C
Rp[disp], Rs
Conditional store with displacement.
SREG[Z]
← SREG[L]
if (SREG[L])
*(Rp+(SE(disp16)))
← Rs
1
stdsp
C
SP[disp], Rs
Store with displacement from SP.
*( (SP && 0xFFFF_FFFC)
+(ZE(disp7)<<2))
← Rs
1
sthh.w
E
Rp[disp], Rx:<part>,
Ry:<part>
Combine halfwords to word and store with
displacement.
*(Rp+(ZE(disp8)<<2))
←
{Rx:<part>, Ry:<part>}
1
E
Rb[Ri<<sa],
Rx:<part>, Ry:<part>
Combine halfwords to word and store
indexed.
*(Rb+(Ri << sa2))
← {Rx:<part>,
Ry:<part>}
1
Table 9-10.
Load/Store Operations (Continued)