參數(shù)資料
型號: SAA2503
廠商: NXP Semiconductors N.V.
英文描述: MPEG2 audio decoder(MPEG2 音頻譯碼器)
中文描述: MPEG2音頻解碼器(的MPEG2音頻譯碼器)
文件頁數(shù): 9/20頁
文件大?。?/td> 139K
代理商: SAA2503
1997 Jul 02
9
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
MPEG2 bitstreams
The MPEG2 audio bitstream is received via the I
2
S-bus in
the same format as specified in IEC 1937. The MPEG2
audio bitstream consists of data bursts of 1 frame.
The data is formatted in 16-bit chunks. The time period
until the next frame is filled with logic 0. The serial data is
received by the SAA2503 via the SDI1 pin (pin 66).
For more information on transporting MPEG2 bitstreams
via IEC 958 see IEC 1937.
Linear PCM (LPCM)
I
2
S-
BUS
Linear PCM samples are received in an I
2
S-bus format.
Serial audio data is received via SDI1 (pin 66).
The I
2
S-bus clock is received via SCKR (pin 61) and the
I
2
S-bus word select is received via WSR (pin 65); the
I
2
S-bus clock operates at 64f
s
.
Q
UAD
I
2
S-
BUS
Quad I
2
S-bus is the interface providing audio samples in
LPCM with 4 times the sampling frequency. The interface
is an extension of the I
2
S-bus where the Serial Data Begin
(SDB) indicates the first 2 channels out of 8 channels.
The audio samples are transferred with MSB first, where
each sample occupies 32 bits, filled with logic 0.
The SDB remains HIGH when only 2 channels LPCM or encode bitstreams (in accordance with IEC 1937) are
transferred (Quad I
2
S-bus is equal to I
2
S-bus).
Fig.3 Quad I
2
S-bus frame format.
handbook, full pagewidth
SD
MGK398
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
WS
SDB
SCK
1
2
S-bus clock/Quad 1
2
S-bus clock
1 sampling period
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