參數(shù)資料
型號(hào): SAA2505H-M1
廠商: NXP Semiconductors N.V.
英文描述: Digital multi-channel audio IC DUET
中文描述: 數(shù)字多聲道音頻IC二重奏
文件頁(yè)數(shù): 21/28頁(yè)
文件大?。?/td> 177K
代理商: SAA2505H-M1
1998 Mar 10
21
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
TIMING CHARACTERISTICS
Note
1.
C
bus
= bus line capacitance in pF.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Serial digital inputs and outputs;
(see Fig.9)
t
r
t
f
T
cy
t
BCK(H)
t
BCK(L)
t
s;DAT
t
s;DAT
t
h;DAT
t
h;DAT
t
s;WS
t
h;WS
t
d;DAT
t
d;WS
rise time
fall time
bit clock cycle time
bit clock time HIGH
bit clock time LOW
data set-up time host
data set-up time I
2
S-bus input
data hold time host
data hold time I
2
S-bus input
word select set-up time I
2
S-bus input
word select hold time I
2
S-bus input
data delay time host
word select delay time host
T
cy
= 50 ns
T
cy
= 50 ns
70
17.5
17.5
320
10
50
10
100
100
7.5
7.5
20
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
cy
= 50 ns
T
cy
= 50 ns
T
cy
= 50 ns
T
cy
= 50 ns
T
cy
= 50 ns
T
cy
= 50 ns
I
2
C-bus timing;
(see Fig.10)
f
SCL
t
BUF
SCL clock frequency
bus free between a STOP and
START condition
hold time (repeated) start condition;
after this period the first clock pulse is
generated
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated start
condition
data hold time
data set-up time
0
1.3
400
kHz
μ
s
t
HD;STA
0.6
μ
s
t
LOW
t
HIGH
t
SU;STA
1.3
0.6
0.6
μ
s
μ
s
μ
s
t
HD;DAT
t
SU;DAT
0
100
0.9
μ
s
ns
for standard mode I
2
C-bus
system t
SU;DAT
> 250 ns
f
SCL
= 400 kHz
f
SCL
= 100 kHz
t
r
rise time of both SDA and SCL
signals
20 + 0.1C
bus(1)
300
20 + 0.1C
bus(1)
1000
20 + 0.1C
bus(1)
300
0.6
0
ns
ns
ns
μ
s
pF
ns
t
f
t
SU;STO
C
L(bus)
t
SP
fall time of both SDA and SCL signals
set-up time for STOP condition
capacitive load for each bus line
pulse width of spikes which must be
suppressed by the input filter
400
50
f
SCL
= 400 kHz
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