- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372109 > SAA3323 (NXP Semiconductors N.V.) Drive processor for DCC systems PDF資料下載
參數(shù)資料
| 型號： | SAA3323 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | 戴納信貸驅(qū)動處理器的系統(tǒng) |
| 文件頁數(shù)： | 24/56頁 |
| 文件大小： | 274K |
| 代理商： | SAA3323 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
May 1994
24
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Read/write connections
TCLOCK
This output pin is the 3.072 MHz clock output for the read
and write amplifiers, it should be connected directly to the
WCLOCK pin of the write amplifier and to the RDCLK pin
of the read amplifier.
RDMUX
This input pin carries the time multiplexed analog tape
channel signals from the read amplifier.
V
ref(n)
AND
V
ref(p)
These are the lower and upper voltage reference inputs for
the ADC in the digital equalizer part of SAA3323.
BIAS
This pin defines a bias current for the ADC. It should be
connected to the analog supply voltage V
DDA
via a 47 k
resistor.
RDSYNC
This output line provides synchronization information for
the read Amplifier data transfers. The relationship between
TCLOCK, RDSYNC and the channel information carried
by the RDMUX line is given in Fig.20. This pin should be
connected directly to the RDSYNC pin of the read
amplifier. When the digital equalizer in SAA3323 is in
search mode this pin will be HIGH ensuring that only the
AUX channel is processed by the SAA3323.
WDATA
This output pin is the multiplexed data and control line for
the write amplifier. Figure 21 shows the manner in which
this information is multiplexed onto WDATA. The WDATA
pin should be connected directly to the WDATA pin of the
write amplifier.
Fig.20 RDMUX, RDSYNC and TCLOCK timing.
handbook, full pagewidth
TCLOCK
RDSYNC
RDMUX
C
C
C
C
C
C
C
C
A
C
C
C
C
C
C
C
C
A
C
C
C
C
C
C
C
C
A
MGB396
Fig.21 WDATA and TCLOCK timing.
handbook, full pagewidth
WDATA
T
MGB397
T
T
T
T
T
T
T
T
T
T
T
SYNC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA3323GP | Drive processor for DCC systems |
| SAA3323H | Drive processor for DCC systems |
| SAA3500H | Digital audio broadcast channel decoder |
| SAA4700T | VPS dataline processor |
| SAA4700 | VPS dataline processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA3323GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Drive processor for DCC systems |
| SAA3323H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Drive processor for DCC systems |
| SAA33299003 | 制造商:LG Corporation 功能描述:S/W,Firmware |
| SAA33308202 | 制造商:LG Corporation 功能描述:S/W,Firmware |
| SAA33333703 | 制造商:LG Corporation 功能描述:S/W,Firmware |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。