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參數(shù)資料
| 型號： | SAA3323GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 274K |
| 代理商： | SAA3323GP |
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May 1994
15
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
handbook, full pagewidth
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SBWS(in)
SBDA(out)
MGB383
SBCL(in)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SBWS(in)
SBDA(out)
SBCL(in)
SBWS(in)
SBDA(out)
bit number
SBEF(out)
SBEF(out)
SBDA(out)
40 ns
tMCLK
tMCLK
V
V
IL
IH
VOH
VOL
VOH
VOL
V
V
IL
IH
2 x tMCLK
Fig.7 Sub-band serial PASC interface timing in play modes; DRPMAS = logic 0.
SBMCLK
This is the sub-band master clock input for the sub-band
serial PASC interface. The frequency of this signal is
nominally 6.144 MHz. When the SAA3323 is used with
SAA2003 this pin is tied to ground, and the TFE settings
bit ‘DRPMAS’ set to logic 1.
SBDIR
This output pin is the sub-band serial PASC bus direction
signal, it indicates the direction of transfer on the sub-band
serial PASC bus. This pin connects directly to the SBDIR
pin on the SAA2003. The transfer directions are shown in
Table 13.
Table 13
PASC bus transfer directions.
SBDIR
DIRECTION
1
0
SAA3323 to SAA2003 transfer (audio play)
SAA2003 to SAA3323 transfer (audio record)
SBCL
This input/output pin is the bit clock line for the sub-band
serial PASC interface to the SAA2003. When used with
SAA2003 this pin is input only. It has a nominal frequency
of 768 kHz.
SBWS
This input/output pin is the word select line for the
sub-band serial PASC interface to the SAA2003. When
used with SAA2003 this pin is input only. It has a nominal
frequency of 12 kHz.
SBDA
This input/output pin is the serial data line for the sub-band
serial PASC interface to the SAA2003.
SBEF
This active HIGH output pin is the error-per-byte line for
the sub-band serial PASC interface to the SAA2003.
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