參數(shù)資料
型號(hào)： SAA4952WP
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Memory controller
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝： PLASTIC, SOT-187, LCC-44
文件頁(yè)數(shù)： 18/32頁(yè)
文件大小： 159K
代理商： SAA4952WP
1997 Jun 10
18
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
The vertical display signal can be programmed in a range
of Nr, Nf from 1 to 511. The setting should correspond to
the source (PAL, NTSC) and the expected standard field
length. For the display the vertical read window should not
exceed the write window. In the event of non-standard
sources with shortened field lengths the memory controller
disables the vertical control signals if the programmed
STOP setting cannot be reached.
LLDFL
The input signal LLDFL is the main line-locked clock pulse
for the display and deflection part generated by an external
PLL circuit. The frequency of LLDFL is 27, 32 or 36 MHz
for a two-clock system. It is fixed to 27 MHz if the
three-clock system is chosen. In this mode, display clocks
of 32 and 36 MHz are generated by an extra display PLL.
The PLL circuit operates on the burst key pulse (ABK) of
the acquisition part and the horizontal reference signal
HRDFL generated by the deflection part of the memory
controller.
The LLDFL should not fall below 24 MHz because this
clock is used to sample the input signals at the memory
controller port (P0 to P7), ALE and WRD.
HRDFL
This horizontal output signal is the reference pulse for the
horizontal deflection drive signal HDFL. The duty cycle of
HRDFL is 50% and the cycle time is 64
μ
s (PAL). For the
golden SCART mode the cycle time is reduced to 32
μ
s.
VDFL
This is the vertical synchronization output signal generated
by the vertical deflection part of the memory controller.
The timing reference of VDFL is the LOW-to-HIGH
transition of the vertical acquisition input pulse VACQ.
Normally VDFL has a pulse width of 2.5
×
HDFL = 80
μ
s
and a cycle time of 100 Hz.
HDFL
The output signal HDFL is used for driving the connected
horizontal deflection circuit. HDFL has a cycle time of
32
μ
s and a pulse width of 64
×
LLDFL = 2.37
μ
s in the 2f
H
mode (see Fig.8).
Control inputs and outputs
ALE
The address latch enable input signal ALE is provided by
the microcontroller. A falling edge of ALE denotes a valid
address.
WRD
This is the write/read enable control signal supplied by the
microcontroller. The HIGH-to-LOW transition of WRD
indicates valid data.
P0
TO
P7
The SAA4952WP is controlled by the bidirectional parallel
port bus P0 to P7 of a microcontroller. Address and data
are transmitted sequentially on the parallel bus.
TEST
The TEST input pin has to be connected to ground.
SDP
The SDP input pin has to be connected to ground for a
three-clock system. This configuration has to be chosen if
the TDA9151 is controlling the deflection. Connecting SDP
to the supply voltage switches the memory controller into
the two-clock mode.
Table 16
SDP mode pin setting
SSC
The Select Single Clock (SSC) control pin has to be
connected to ground to activate a 2f
H
mode and a multi
clock system. For the 50 Hz/1f
H
mode in a single clock
system the input is connected to the supply (V
DD
).
Table 17
SCC mode pin setting
T
IMING SPECIFICATION
The internal delays of the output signals referenced to the
respective clock are given in Table 18.
SDP
REMARK
0
1
three-clock system; supports TDA9151
two-clock system
SCC
REMARK
0
2f
H
mode (100/120 Hz; progressive scan);
two-clock or three-clock system
1f
H
mode (50/60 Hz; 15.625/15.75 kHz);
single clock system
1
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