參數(shù)資料
型號(hào)： SAA5252T
廠商： NXP SEMICONDUCTORS
元件分類： 圖文
英文描述： Line twenty-one acquisition and display LITOD
中文描述： TELETEXT DECODER, PDSO24
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 203K
代理商： SAA5252T
1996 Jul 18
13
Philips Semiconductors
Product specification
Line twenty-one acquisition and display (LITOD)
SAA5252
I
2
C INTERFACE
Description of WRITE registers
The write subaddresses auto increment from 0 through to 4 at which point they stay until a new write subaddress is sent.
Registers are set to all logic 0 at power-up.
Table 3
Register 0 WRITE (Control Byte 1)
Table 4
Register 1 WRITE (Control Byte 2)
Table 5
Register 2 WRITE (On-Screen Display data row address)
Table 6
Register 3 WRITE (On-Screen Display data column address)
Table 7
Register 4 WRITE (On-Screen Display data)
BIT
DESCRIPTION
D0 to D3
D4
D5
D6
D7
H0 to H3 set the offset position from the start of the horizontal sync pulse, set to a nominal value on reset.
Vertical sync pulse expected to be negative going logic 0 or positive-going logic 1.
Horizontal sync pulse expected to be negative going logic 0 or positive-going logic 1.
Video outputs will be positive going logic 0 or negative-going logic 1.
Data field select. When set to logic 0 Field 1 is decoded, when set to logic 1 Field 2 is decoded.
BIT
DESCRIPTION
D0, D1
D2, D3
D4
Display mode selection bits. Table 8 shows the possible display modes.
Enhanced caption mode selection bits. Table 9 shows the possible enhanced caption modes.
When set to logic 1 acquisition of caption data is inhibited to allow the display to be used for
On-Screen Display purposes.
Acquisition window selection. When set to logic 0 only Line 21 is checked for caption data. When set to
logic 1, lines 19 to 23 of both fields are checked, allowing encrypted video signals to be handled.
User channel selection.
Clears the page memory when set HIGH. The page memory will be within two fields (30 ms).
D5
D6
D7
BIT
DESCRIPTION
D0 to D3
Row 0 to 3 sets the row address for On-Screen Display. This stored value will be incremented by overflow
increments of Register 3.
BIT
DESCRIPTION
D0 to D4
Columns 0 to 4 sets the column address for On-Screen Display. This stored value will be incremented by
writes to Register 4.
BIT
DESCRIPTION
D0 to D6
OSD0 to OSD6, On-Screen Display data bits writing to this register causes Register 3 to increment its
stored value.
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