參數(shù)資料
型號: SAA5252T
廠商: NXP SEMICONDUCTORS
元件分類: 圖文
英文描述: Line twenty-one acquisition and display LITOD
中文描述: TELETEXT DECODER, PDSO24
文件頁數(shù): 14/20頁
文件大?。?/td> 203K
代理商: SAA5252T
1996 Jul 18
14
Philips Semiconductors
Product specification
Line twenty-one acquisition and display (LITOD)
SAA5252
Table 8
Display modes
Table 9
Enhanced caption modes
Description of READ registers
The read subaddresses auto increment from 80H through to 82H at which point they stay until a new read subaddress
is sent.
All the bits in Table 10 are reset to logic 0 after the register is read.
Table 10
Register 80H READ (status)
Table 11
Register 81H READ (first data byte)
Note
1.
In the Line 21, specification data bits are numbered D1 to D8.
Table 12
Register 82H READ (second data byte)
Note
1.
In the Line 21, specification data bits are numbered D1 to D8.
DISPLAY MODE OPTIONS
M1
M0
Video only
Text mode
Normal caption mode
Enhanced caption mode
0
0
1
1
0
1
0
1
ENHANCED CAPTION MODES
EN1
EN0
Enhanced caption modes
Shadowed character/Video background
Shadowed character/Mesh background
Normal character/Video background
Normal character/Mesh background
EN1
0
0
1
1
EN0
0
1
0
1
BIT
DESCRIPTION
D0
D1
D2
D3
D7
Data ready (new data has been acquired).
Parity error shut-down, goes HIGH when SAA5252 has a parity shut-down condition.
Indicates the following bytes are extended data service bytes.
Indicates Field 1 or Field 2 data bytes.
Indicates Power-On Reset (POR) has occurred, all I
2
C-bus write registers have been reset to logic 0.
BIT
DESCRIPTION
D0 to D6
D7
Data Bit 1 to Data Bit 7 (see note 1).
Parity error flag bit. Bit goes HIGH when a parity error has occurred.
BIT
DESCRIPTION
D0 to D6
D7
Data Bit 1 to Data Bit 7 (see note 1).
Parity error flag bit. Bit goes HIGH when a parity error has occurred.
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