參數(shù)資料
型號： SAA569x
廠商： NXP Semiconductors N.V.
英文描述： Enhanced TV microcontrollers with On-Screen Display (OSD)
中文描述： 與微控制器在強化電視屏幕顯示（OSD）
文件頁數(shù)： 40/116頁
文件大?。?/td> 532K
代理商： SAA569X
2002 May 06
40
Philips Semiconductors
Objective specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA567x; SAA569x
There are four interrupts connected to the 80C51
microcontroller peripherals, as follows:
I
2
C-bus Transmit/Receive
UART Receive
UART Transmit
UART Receive/Transmit.
Four additional general purpose external interrupts are
incorporated in the SAA567x; SAA569x with
programmable edge detection (INT2 {EX2}, INT3 {EX3},
INT4 {EX4} and INT5 {EX5}). The EXTINT SFR is used to
configure each of these interrupts as either level activated,
rising edge, falling edge or both edges sensitive, see
Table 11.
12.1
Interrupt enable structure
Each of the individual interrupts can be enabled or
disabled by setting or clearing the relevant bit in the
interrupt enable SFRs (IE and IEN1). All interrupt sources
can also be globally disabled by clearing bit EA (IE.7), as
shown in Fig.10.
12.2
Interrupt enable priority
Each interrupt source can be assigned one of two priority
levels. The interrupt priorities are defined by the interrupt
priority SFRs (IP and IP1).
A low priority interrupt can be interrupted by a high priority
interrupt, but not by another low priority interrupt. A high
priority interrupt cannot be interrupted by any other
interrupt source.
If two requests of different priority level are received
simultaneously, the request with the higher priority level is
serviced. If requests of the same priority level are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined by the
polling sequence as defined in Table 13.
12.3
Interrupt vector address
The processor acknowledges an interrupt request by
executing a hardware generated LCALL to the appropriate
servicing routine. The interrupt vector addresses for each
source are shown in Table 13.
12.4
Level/edge interrupt
The external interrupt can be programmed to be either
level activated or transition activated by setting or clearing
the IT0/IT1 bits in the Timer Control SFR (TCON), see
Table 12.
The external interrupt INT1 differs from the standard
80C51 interrupt in that it is activated on both edges when
in edge sensitive mode. This is to allow software pulse
width measurement for handling remote control inputs.
The four other external interrupts INT2, INT3, INT4 and
INT5 are configured using the EXTINT register, as shown
in Table 11.
Table 11
Configuration of external interrupts
(INT2 to INT5)
Table 12
External interrupt activation
SFR EXTINT;
EXnCFG<1:0>;
n = 2 to 5
MODE
00
01
10
11
level sensitive - active LOW
rising edge sensitive
falling edge sensitive
both edges sensitive
BIT
LEVEL
EDGE
IT0
IT1
active LOW
INT0 = negative edge
INT1 = positive and negative edge
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