參數(shù)資料
型號： SAA569x
廠商： NXP Semiconductors N.V.
英文描述： Enhanced TV microcontrollers with On-Screen Display (OSD)
中文描述： 與微控制器在強化電視屏幕顯示（OSD）
文件頁數(shù)： 7/116頁
文件大?。?/td> 532K
代理商： SAA569X
2002 May 06
7
Philips Semiconductors
Objective specification
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA567x; SAA569x
6.2
Pin description
Table 1
LQFP100 package
SYMBOL
PIN
TYPE
DESCRIPTION
P2.0/TPWM
P2.1/PWM0
P2.2/PWM1
P2.3/PWM2
P2.4/PWM3
P2.5/PWM4
P2.6/PWM5
P2.7/PWM6
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
P3.4/PWM7/T2EX
P3.5/INT5
P3.6
P3.7
V
SSC
P0.0/RX
P0.1/TX
P0.2/INT2
P0.3/INT3
P0.4/INT4
P0.5
P0.6
P0.7/T2
V
SSA
CVBS0
CVBS1
SYNC_FILTER
100
93
94
95
96
97
98
1
2
4
5
6
44
54
59
25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
Port 2:
8-bit programmable bidirectional port with alternative functions.
P2.0/TPWM is the output for the 14-bit high precision PWM; P2.1/PWM0 to
P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6
Port 3:
8-bit programmable bidirectional port with alternative functions.
P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility;
P3.4/PWM7/T2EX is the output for the 6-bit PWM7 or the Timer 2 control;
P3.5/INT5 is the external Interrupt 5; P3.6 and P3.7 have no alternative
functions
11, 62, 99
16
17
18
22
24
13
28
29
30
31
32
34
core ground
Port 0:
8-bit programmable bidirectional port (with alternative functions).
P0.0/RX and P0.1/TX are respectively the serial transmit and receive lines
for the UART; P0.2/INT2 to P0.4/INT4 are the external interrupts 2 to 4;
P0.5 and P0.6 have no alternative functions and have 8 mA current sinking
capability for direct drive of LEDs
analog ground
2 composite video inputs selectable via SFR; a positive-going 1 V
(peak-to-peak) input is required and connected via a 100 nF capacitor
CVBS sync filter input; this pin should be connected to V
SSA
via a 100 nF
capacitor
reference current input for analog circuits and connected to V
SSA
via a
24 k
resistor
de-interlace output synchronized with the VSYNC pulse to produce a
non-interlaced display by adjustment of the vertical deflection circuits
OTP programming voltage
open-drain, active LOW output which allows selective contrast reduction of
the TV picture to enhance a mixed mode display
3.3 V analog power supply
pixel rate output of the BLUE colour information
IREF
35
I
FRAME
41
O
VPE
COR
21, 42
43
I
O
V
DDA
B
45
46
O
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