![](http://datasheet.mmic.net.cn/390000/SAA6713AH_datasheet_16832284/SAA6713AH_9.png)
2004 Apr 05
9
Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
V
SSD(IC8)
V
DDD(IC8)
V
SSD(EP8)
V
DDD(EP8)
CSG3
CSG4/A1
122
123
124
125
126
127
O
I/O
internal digital core supply ground 8
internal digital core supply voltage 8 (2.5 V)
external digital pad supply ground 8
external digital pad supply voltage 8 (3.3 V)
control signal generator 3 output
control signal generator 4 output (CSG4) or I
2
C-bus slave address input, latched
via hardware reset (A1)
control signal generator 5 output
control signal generator 6 output
control signal generator 7 output
external digital pad supply ground 9
external digital pad supply voltage 9 (3.3 V)
control signal generator 8 output
control signal generator 9 output
sample clock input or output; configurable as output if generated internally
data inversion output of ports A, B and C
data inversion output of ports D, E and F
output enable status output
pulse width modulation for control of backlight brightness output
vertical sync input or output; configurable as output if decoded from composite
sync
horizontal and composite sync input
external digital pad supply ground 10
external digital pad supply voltage 10 (3.3 V)
internal digital core supply ground 9
internal digital core supply voltage 9 (2.5 V)
supply ground for panel clock phase locked loop
supply voltage for panel clock phase locked loop (2.5 V)
do not connect
analog supply ground for sample clock phase locked loop
analog supply voltage for sample clock phase locked loop (2.5 V)
digital supply ground for sample clock phase locked loop
digital supply voltage for sample clock phase locked loop (2.5 V)
test reset input for boundary scan test (active LOW); note 2
test clock input for boundary scan test; note 2
test data input for boundary scan test; note 2
test mode select input for boundary scan test or scan test; note 2
test data output for boundary scan test
CSG5
CSG6
CSG7
V
SSD(EP9)
V
DDD(EP9)
CSG8
CSG9
VCLK
INVA
INVB
OUTEN
PWM
VSYNC
128
129
130
131
132
133
134
135
136
137
138
139
140
O
O
O
O
O
I/O
O
O
O
O
I/O
HSYNC
V
SSD(EP10)
V
DDD(EP10)
V
SSD(IC9)
V
DDD(IC9)
V
SS(PLL)(P)
V
DD(PLL)(P)
n.c.
V
SSA(PLL)(S)
V
DDA(PLL)(S)
V
SSD(PLL)(S)
V
DDD(PLL)(S)
TRST
TCK
TDI
TMS
TDO
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
I
I
I
I
I
O
SYMBOL
PIN
(1)
TYPE
DESCRIPTION