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參數(shù)資料
| 型號： | SAA6721 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | SXGA RGB to TFT graphics engine |
| 中文描述： | SXGA RGB到液晶圖形引擎 |
| 文件頁數(shù)： | 43/72頁 |
| 文件大?。?/td> | 360K |
| 代理商： | SAA6721 |
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1999 May 11
43
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
H
ORIZONTAL DELAY OF END OF VERTICAL SYNC
Horizontal end delay of vertical sync pulse at pin PVS
218 and 219
W
D10 to D0
H
ORIZONTAL SYNC PULSE START
Start of horizontal sync pulse at pin PHS
220 and 221
W
D10 to D0
H
ORIZONTAL SYNC PULSE END
End of horizontal sync pulse at pin PHS
222 and 223
W
D10 to D0
D
ATA QUALIFIER START
Start of border region and horizontal data qualifier at pin PDE
224 and 225
W
D10 to D0
D
ATA QUALIFIER END
End of border region and horizontal data qualifier at pin PDE
226 and 227
W
D10 to D0
H
ORIZONTAL ACTIVE REGION START
Start of horizontal active video region
228 and 229
W
D10 to D0
V
ERTICAL SYNC PULSE END
Vertical sync pulse end at pin PVS
230 and 231
W
D10 to D0
M
AXIMUM HORIZONTAL LINE LENGTH
Maximum reachable line length for length controlling
232 and 233
W
D10 to D0
NAME
SUBADDRESS
R/W
DATA
8.2
Clock management
8.2.1
C
LOCK GENERATION AND MULTIPLEXING
For normal operation the SAA6721E uses two clock
inputs; pin VCLK and pin CLK. VCLK is used as the
sample clock provided by the external ADCs or decoder.
The frequency and the sample edges of this clock depend
on the number of ADCs connected, or on the video dot
clock:
1 ADC mode: maximum VCLK frequency is 150 MHz
2 ADC mode: maximum VCLK frequency is 75 MHz.
The clock from pin CLK is used as an internal reference,
and it is the source clock for the internal PLL. The memory
clock MCLKO and panel clock PCLK are derived from the
PLL (see Fig.11):
N
M
Where N = pre-divider ratio, M = post-divider ratio and
N
MCLKO
N
16
×
=
PCLK
CLK
32
------
×
=
5 MHz
CLK
8 MHz
≤
≤
It is possible to drive the memory clock output directly
without the internal PLL via pin MCLKI. To achieve this the
programming flag pll_mclk must be set to logic 0.
The same is possible for the panel output clock. Therefore
the system clock CLK is used directly. The system clock is
controlled by pll_pclk which must be set to logic 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6721E | SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎) |
| SAA6750 | Encoder for MPEG2 image recording EMPIRE |
| SAA6750H | Encoder for MPEG2 image recording EMPIRE |
| SAA6752HS | MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA7102 | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:12; Connector Shell Size:28; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6721E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
| SAA6750 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
| SAA6750H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
| SAA6752HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA6752HS/V103 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
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