參數(shù)資料
型號(hào): SAA7104H
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: GT 38C 38#12 PIN PLUG
中文描述: COLOR SIGNAL ENCODER, PQFP64
封裝: 14 X 14 MM, 2.70 MM HEIGHT, PLASTIC, MS-022, SOT-393-1, QFP-64
文件頁數(shù): 30/71頁
文件大?。?/td> 354K
代理商: SAA7104H
2004 Mar 04
30
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 27
Subaddress 1BH
Table 28
Subaddresses 26H and 27H
Table 29
Subaddress 28H
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
MSM
0
1
0
monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset
monitor sense mode on
automatic monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default
after reset
automatic monitor sense mode on if MSM = 0
pin TVD is active
pin TVD is 3-state; default after reset
check comparator at DAC on pin RED_CR_C_CVBS is active, output is loaded
check comparator at DAC on pin RED_CR_C_CVBS is inactive, output is not loaded
check comparator at DAC on pin GREEN_VBS_CVBS is active, output is loaded
check comparator at DAC on pin GREEN_VBS_CVBS is inactive, output is not loaded
check comparator at DAC on pin BLUE_CB_CVBS is active, output is loaded
check comparator at DAC on pin BLUE_CB_CVBS is inactive, output is not loaded
MSA
1
0
1
0
1
0
1
0
1
MSOE
RCOMP
(read only)
GCOMP
(read only)
BCOMP
(read only)
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
WSS
wide screen signalling bits
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
wide screen signalling output is disabled; default after reset
wide screen signalling output is enabled
WSSON
0
1
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
REMARKS
BS
starting point of burst in clock cycles
PAL: BS = 33 (21H); default after reset if
strapping pin FSVGC tied to HIGH
NTSC: BS = 25 (19H); default after reset if
strapping pin FSVGC tied to LOW
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