參數(shù)資料
型號(hào): SAA7104H
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: GT 38C 38#12 PIN PLUG
中文描述: COLOR SIGNAL ENCODER, PQFP64
封裝: 14 X 14 MM, 2.70 MM HEIGHT, PLASTIC, MS-022, SOT-393-1, QFP-64
文件頁數(shù): 7/71頁
文件大?。?/td> 354K
代理商: SAA7104H
2004 Mar 04
7
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Notes
1.
2.
Pin type: I = input, O = output, S = supply, pu = pull-up.
In accordance with the “IEEE1149.1”standard the pins TDI, TMS, TCK and TRST are input pins with an internal
pull-up resistor and TDO is a 3-state output pin.
The pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1.
For board design without boundary scan implementation connect TRST to ground.
This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test
Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
3.
4.
5.
SRES
VSM
HSM_CSYNC
38
39
40
I/O
O
O
sync reset input
vertical synchronization output to monitor (non-interlaced auxiliary RGB)
horizontal synchronization output to monitor (non-interlaced auxiliary RGB) or
composite sync for RGB-SCART
analog output of RED or C
R
or C or CVBS signal
analog output of GREEN or VBS or CVBS signal
analog supply voltage 1 (3.3 V for DACs)
analog supply voltage 2 (3.3 V for DACs)
analog output of BLUE or C
B
or CVBS signal
DAC reference pin; connected via 1 k
resistor to analog ground (do not use
capacitor in parallel with 1 k
resistor)
DAC reference pin; connected via 12
resistor to analog ground
analog ground 1
analog ground 2
crystal oscillator output
crystal oscillator input
analog supply voltage 3 (3.3 V for oscillator)
analog supply voltage 4 (3.3 V)
interrupt if TV is detected at DAC output
test reset input for BST; active LOW; notes 2, 4 and 5
test data input for BST; note 2
digital ground 4
digital supply voltage 4 (3.3 V for core)
teletext request output or 13.5 MHz clock output of the crystal oscillator; note 3
teletext input or sync reset input
MSB
3 with C
B
-Y-C
R
4 : 2 : 2; see Tables 8 to 13 for pin assignment
MSB
2 with C
B
-Y-C
R
4 : 2 : 2; see Tables 8 to 13 for pin assignment
MSB
1 with C
B
-Y-C
R
4 : 2 : 2; see Tables 8 to 13 for pin assignment
MSB with C
B
-Y-C
R
4 : 2 : 2; see Tables 8 to 13 for pin assignment
RED_CR_C_CVBS
GREEN_VBS_CVBS
V
DDA1
V
DDA2
BLUE_CB_CVBS
RSET
41
42
43
44
45
46
O
O
S
S
O
O
DUMP
V
SSA1
V
SSA2
XTALO
XTALI
V
DDA3
V
DDA4
TVD
TRST
TDI
V
SSD4
V
DDD4
TTXRQ_XCLKO2
TTX_SRES
PD4
PD5
PD6
PD7
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
O
S
S
O
I
S
S
O
I/pu
I
S
S
O
I
I
I
I
I
SYMBOL
PIN TYPE
(1)
DESCRIPTION
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