參數(shù)資料
型號: SAA7105H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Digital video encoder
文件頁數(shù): 42/71頁
文件大?。?/td> 354K
代理商: SAA7105H
2004 Mar 04
42
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 73
Subaddresses 91H and 94H
Table 74
Subaddresses 92H and 94H
Table 75
Subaddresses 93H and 94H
Table 76
Subaddresses 95H and 96H
Table 77
Subaddress 96H
DATA BYTE
DESCRIPTION
XPIX
pixel in X direction; defines half the number of active pixels per input line (identical to the length of
CBO pulses)
DATA BYTE
DESCRIPTION
YOFSO
vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually,
YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
DATA BYTE
DESCRIPTION
YOFSE
vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually,
YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
DATA BYTE
DESCRIPTION
YPIX
defines the number of requested input lines from the feeding device;
number of requested lines = YPIX + YOFSE
YOFSO
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
EFS
0
1
0
1
0
1
0
1
0
1
frame sync signal at pin FSVGC ignored in slave mode
frame sync signal at pin FSVGC accepted in slave mode
normal polarity of CBO signal (HIGH during active video)
inverted polarity of CBO signal (LOW during active video)
the SAA7104H; SAA7105H is timing master to the graphics controller
the SAA7104H; SAA7105H is timing slave to the graphics controller
if hardware cursor insertion is active, set LOW for non-interlaced input signals
if hardware cursor insertion is active, set HIGH for interlaced input signals
luminance sharpness booster disabled
luminance sharpness booster enabled
PCBN
SLAVE
ILC
YFIL
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