參數(shù)資料
型號(hào): SAA7114H
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI data slicer and high performance scaler
中文描述: COLOR SIGNAL DECODER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁數(shù): 34/147頁
文件大?。?/td> 759K
代理商: SAA7114H
2004 Mar 03
34
Philips Semiconductors
Product specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI data slicer and high performance scaler
SAA7114
8.1.5
C
LOCK GENERATION CIRCUIT
The internal CGC generates all clock signals required for
the video input processor.
The internal signal LFCO is a digital-to-analog converted
signal provided by the horizontal PLL. It is the multiple of
the line frequency:
6.75 MHz = 429
×
f
H
(50 Hz), or
6.75 MHz = 432
×
f
H
(60 Hz).
The LFCO signal is multiplied by a factor of 2 and 4 in the
internalPLLcircuit(includingphasedetector,loopfiltering,
VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50% duty
factor.
Table 3
Decoder clock frequencies
CLOCK
FREQUENCY (MHz)
XTALO
LLC
LLC2
LLC4 (internal)
LLC8 (virtual)
24.576 or 32.110
27
13.5
6.75
3.375
Fig.20 Block diagram of the clock generation circuit.
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
LOOP
FILTER
DIVIDER
1/2
DIVIDER
1/2
OSCILLATOR
MHB330
LLC2
LLC
LFCO
8.1.6
P
OWER
-
ON RESET AND
C
HIP
E
NABLE
(CE)
INPUT
A missing clock, insufficient digital or analog V
DDA0
supply
voltages (below 2.7 V) will start the reset sequence; all
outputs are forced to 3-state (see Fig.21). The indicator
output RES is LOW for approximately 128 LLC after the
internal reset and can be applied to reset other circuits of
the digital TV system.
It is possible to force a reset by pulling the Chip Enable pin
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2 and SDA
return from 3-state to active, while the other signals have
to be activated via programming.
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