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參數(shù)資料
| 型號： | SAA7187 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital video encoder (DENC2-SQ)(數(shù)字視頻編碼器) |
| 中文描述： | 數(shù)字視頻編碼器（DENC2 -倚）（數(shù)字視頻編碼器） |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 197K |
| 代理商： | SAA7187 |
Philips Semiconductors
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
May 1994
11
6.0
Figure 4 points out several of those features
that can be realized in an application with
SAA7188A (or SAA7187). Two or more digital
video encoder devices can be locked to each
other. All their analog video outputs are
completely in phase: horizontally, vertically
and also the subcarrier. One of the devices
functions as timing master, the other ones
work in sync slave mode. The master device
provides on RCM1 the color field sequence
indication signal FSEQ, which transports
horizontal and vertical reference as well as
subcarrier phase reference via the color field
sequence indication. The RCV1 inputs of the
other devices are set to FSEQ function and
also used to trigger line timing. VTRIG and
HTRIG are both set to zero.
APPLICATION EXAMPLE
RCM2 output of the master device can be
freely defined in horizontal timing. By that it
can be used as input data gating signal
(HREF–gate) at the RCV2 inputs of the other
encoder devices. This RCM2 output signal of
the master device (or of each device) could
also be fed back to its own RCV2 input for
input data gating function.
RCM1 and RCM2 outputs of the slave
devices can be used as trigger and timing
signals for the digital video signal sources.
RCM1 can be chosen as a vertical sync, or
as an odd/even signal. RCM2 can be defined
as an HS for trigger and counting purposes,
or it can be used as a source gating signal. It
can be placed ‘early’ to compensate for
pipeline delay on the data delivery side, such
as memory access, etc.
If the RCV2 pins of the slave (and/or the
master) device are not used as gating input,
they could be switched to output, and could
be used as (early) enabling signal (CBN) at
the signal source. In that case even VBI
blanking is supported. (This option is not
shown in Figure 4).
The digital encoder that works as timing
master in the configuration of Figure 4 can be
genlocked to an analog video reference
signal via digital encoder circuitry. For this
purpose, the SAA7188A can be combined
with the SAA7151B, SAA7157 and
TDA8708/09. The SAA7187 can be
combined with the SAA7191B, SAA7197 and
TDA8708/09 or with the SAA7110. The digital
real-time decoder system locks itself to the
analog reference video signal and generates
line-locked clock, horizontal and vertical sync
signals, and the real-time control signal RTC.
If the encoder runs with the line-locked clock
of the decoder, it is important to also have the
RTC wire connected, in order to maintain the
correct subcarrier frequency in the encoder,
same as in the analog reference signal. To
have the same clock at both the decoder and
encoder side is very interesting in some
applications; for example, as a frame buffer
as it avoids the complications of an
asynchronous two-clock system.
The SAA7151B or other decoder can provide
a pair of vertical and horizontal syncs as VS
and HS, or provide an odd/even signal FS
(“ODD” on pin 39 of SAA7151B, for example)
to synchronize the digital encoder to the
reference video signal, and also into the
correct interlace sequence. Proper
programming of HTRIG and VTRIG can
adjust pipeline processing delay in decoder
and/or frame buffer circuitry. If FS from the
decoder is used as RCV1 input for the first
“master” encoder, it can also be utilized as a
horizontal reference signal. Then RCV2 is
free to be used as gating input, fed by the
RCM2 output, or it can be switched to output
a CBN-like signal to one of the video signal
sources.
Figure 4 shows a rather complex system,
but the various timing techniques, as
discussed above, can be applied in simpler
systems, too.
相關PDF資料 |
PDF描述 |
|---|---|
| SAA7188A | Digital Video Encoder (DENC2-M)(數(shù)字視頻編碼器(DENC2-M)) |
| SAA7201 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7201H | Integrated MPEG2 AVG decoder |
| SAA7212 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7212H | Integrated MPEG AVG decoder |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7187WP | 制造商:NXP Semiconductors 功能描述: |
| SAA7188 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC2-M |
| SAA7188A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC2-M |
| SAA7188AWP | 制造商:NXP Semiconductors 功能描述:COLOR SIGNAL ENCODER, PQCC68 |
| SAA7191B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Multistandard Colour Decoder, Square Pixel DMSD-SQP |
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