- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385813 > SAA7188A (NXP Semiconductors N.V.) Digital Video Encoder (DENC2-M)(數(shù)字視頻編碼器(DENC2-M)) PDF資料下載
參數(shù)資料
| 型號： | SAA7188A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital Video Encoder (DENC2-M)(數(shù)字視頻編碼器(DENC2-M)) |
| 中文描述： | 數(shù)字視頻編碼器（DENC2米）（數(shù)字視頻編碼器（DENC2米）） |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 252K |
| 代理商： | SAA7188A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
1996 Jul 08
20
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2-M)
SAA7188A
Table 24
Logic levels and function of CCEN
Table 25
Logic levels and function of SRCM
Table 26
Subaddress 6E to 6F
Table 27
Subaddress 70
Note
1.
If cross-colour reduction is programmed, it is active between FAL and LAL in both events.
DATA BYTE
FUNCTION
CCEN1
CCEN0
0
0
1
1
0
1
0
1
line 21 encoding off
enables encoding in field 1 (odd)
enables encoding in field 2 (even)
enables encoding in both fields
DATA BYTE
AS OUTPUT
FUNCTION
SRCM1
SRCM0
0
0
1
0
1
0
VS
FS
Vertical Sync each field
Frame Sync (odd/even)
Field Sequence, vertical sync every fourth field (FISE = 1) or
eighth field (FISE = 0)
not applicable
FSEQ
1
1
DATA BYTE
DESCRIPTION
HTRIG
sets the Horizontal Trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = 032H
DATA BYTE
LOGIC LEVEL
DESCRIPTION
VTRIG
sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals,
measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
vertical blanking is defined by programming of FAL and LAL
vertical blanking is forced automatically at least during field synchronization and
equalization pulses; note 1
selects the phase reset mode of the colour subcarrier generator; see Table 28
SBLBN
0
1
PHRES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7201 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7201H | Integrated MPEG2 AVG decoder |
| SAA7212 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7212H | Integrated MPEG AVG decoder |
| SAA7219 | MPEG2 Transport RISC Processor(MPEG2 傳送RISC處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7188AWP | 制造商:NXP Semiconductors 功能描述:COLOR SIGNAL ENCODER, PQCC68 |
| SAA7191B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Multistandard Colour Decoder, Square Pixel DMSD-SQP |
| SAA7191WP | 制造商:NXP Semiconductors 功能描述:7191WP |
| SAA7192A/AA68A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
| SAA7192AWP | 制造商:NXP Semiconductors 功能描述:IMAGE PROCESSOR, 68 Pin, Plastic, PLCC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。